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There are open questions that came up while Michael created the great and comprehensive new test_programs/cpu_test.asm. Some of them are described here: #53 (comment) and some of them are described here: #50, #40 and #37
The compromise solution for now is: On the emulator, Bernd already implemented the "non forgetting" SR register and we should also change the hardware accordingly, because this does not seem to break things: #53 (comment)
Still open are topics around the V flag, CMP semantics and other topics.
So this issue is about
Revisiting the ISA
Finally deciding the route
(Here comes the monster loose end): Debug/fix all the existing software, that relies on the "wrong" behaviour, for example of the V flag which is today simply implented as: "adding/subtracting two positive numbers and getting a negative result or adding/subtracting two negative numbers and getting a positive result"
As for the time of creating this issue, we already foresee, that the following might turn out into a large undertaking. So it is labled with "V1.7" as a placeholder for "not in V1.6 but later"
The text was updated successfully, but these errors were encountered:
* The SUB and SUBC instructions generate overflow (V) using a different
algorithm.
* The CMP instruction modifies V, N, and Z using a different algorithm,
and does not change C or X.
These changes should be considered for reverting in V1.7, see Issue #57.
There are open questions that came up while Michael created the great and comprehensive new
test_programs/cpu_test.asm
. Some of them are described here: #53 (comment) and some of them are described here: #50, #40 and #37The compromise solution for now is: On the emulator, Bernd already implemented the "non forgetting" SR register and we should also change the hardware accordingly, because this does not seem to break things: #53 (comment)
Still open are topics around the
V
flag, CMP semantics and other topics.So this issue is about
V
flag which is today simply implented as: "adding/subtracting two positive numbers and getting a negative result or adding/subtracting two negative numbers and getting a positive result"As for the time of creating this issue, we already foresee, that the following might turn out into a large undertaking. So it is labled with "V1.7" as a placeholder for "not in V1.6 but later"
The text was updated successfully, but these errors were encountered: