Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Hardware: Convenient debugging #67

Open
sy2002 opened this issue Aug 17, 2020 · 0 comments
Open

Hardware: Convenient debugging #67

sy2002 opened this issue Aug 17, 2020 · 0 comments
Assignees
Labels

Comments

@sy2002
Copy link
Owner

sy2002 commented Aug 17, 2020

This is a spin-off of #66 . This topic needs to be thought through holistically:

  • Hardware debug module using the interrupt system
  • Monitor enhanements
  • The ideas of Michael, as described in this comment and copy pasted below, including the VGA overlay:

I agree, we need something like this. I tried debugging the latest cpu_test.asm on hardware, and that was quite tedious.

Regarding ncurses I would love to have support for that. It would make porting existing C-programs to QNICE almost trivial in many cases. I do think this is the best long-term solution, i.e. to implement a ncurses library.

Regarding debugging in hardware, I've in previous projects used an VGA overlay, i.e. a virtual layer on top of the current VGA screen that displays all relevant state information of the processor. This would all be implemented in pure VHDL code, and could be enabled/disabled by one of the switches. It would be "simple" to e.g. disassemble ten lines around the current PC, to implement single-step, to set breakpoints, etc.

Something like that can be done in various stages, where the first stage is just to display the current value of R0-R15, the second stage is to disassemble the current instruction, etc. Controlling the execution could be done using the push-buttons.

We still have a way to go before V1.6 is finished, and then we have to decide on, what we would like to include in V1.7. Only then can we give a very rough estimate of when V1.7 might be finished.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

No branches or pull requests

3 participants