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main.lst
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main.lst
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main.elf: file format elf32-msp430
Disassembly of section .text:
0000f800 <__init_stack>:
f800: 31 40 80 02 mov #640, r1 ;#0x0280
0000f804 <__low_level_init>:
f804: 15 42 20 01 mov &0x0120,r5
f808: 75 f3 and.b #-1, r5 ;r3 As==11
f80a: 35 d0 08 5a bis #23048, r5 ;#0x5a08
0000f80e <__do_copy_data>:
f80e: 3f 40 00 00 mov #0, r15 ;#0x0000
f812: 0f 93 tst r15
f814: 07 24 jz $+16 ;abs 0xf824
f816: 82 45 20 01 mov r5, &0x0120
f81a: 2f 83 decd r15
f81c: 9f 4f 32 fa mov -1486(r15),512(r15);0xfa32(r15), 0x0200(r15)
f820: 00 02
f822: f9 23 jnz $-12 ;abs 0xf816
0000f824 <__do_clear_bss>:
f824: 3f 40 08 00 mov #8, r15 ;#0x0008
f828: 0f 93 tst r15
f82a: 06 24 jz $+14 ;abs 0xf838
f82c: 82 45 20 01 mov r5, &0x0120
f830: 1f 83 dec r15
f832: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15)
f836: fa 23 jnz $-10 ;abs 0xf82c
0000f838 <main>:
void candle_init() {
CANDLE_DIR |= CANDLE;
CANDLE_OUT &= ~CANDLE;
}
int main(void) {
f838: 21 83 decd r1
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
f83a: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80
f83e: 20 01
BCSCTL1 = CALBC1_1MHZ; // Set range
f840: d2 42 ff 10 mov.b &0x10ff,&0x0057
f844: 57 00
DCOCTL = CALDCO_1MHZ; // SMCLK = DCO = 1MHz
f846: d2 42 fe 10 mov.b &0x10fe,&0x0056
f84a: 56 00
candle_init();
f84c: b0 12 1c fa call #0xfa1c
uart_init();
f850: b0 12 a2 f8 call #0xf8a2
__enable_interrupt();
f854: 32 d2 eint
uint8_t c;
while(1) {
if(uart_getc(&c)) {
f856: 0f 41 mov r1, r15
f858: b0 12 ba f8 call #0xf8ba
f85c: 4f 93 tst.b r15
f85e: fb 27 jz $-8 ;abs 0xf856
if(c == '1') {
f860: 6f 41 mov.b @r1, r15
f862: 7f 90 31 00 cmp.b #49, r15 ;#0x0031
f866: 05 20 jnz $+12 ;abs 0xf872
CANDLE_OUT |= CANDLE;
f868: d2 d3 21 00 bis.b #1, &0x0021 ;r3 As==01
uart_puts("on");
f86c: 3f 40 28 fa mov #-1496, r15 ;#0xfa28
f870: 08 3c jmp $+18 ;abs 0xf882
uart_putc('\n');
uart_putc('\r');
} else if (c == '0') {
f872: 7f 90 30 00 cmp.b #48, r15 ;#0x0030
f876: ef 23 jnz $-32 ;abs 0xf856
CANDLE_OUT &= ~CANDLE;
f878: f2 f0 fe ff and.b #-2, &0x0021 ;#0xfffe
f87c: 21 00
uart_puts("off");
f87e: 3f 40 2b fa mov #-1493, r15 ;#0xfa2b
f882: b0 12 1a f9 call #0xf91a
uart_putc('\n');
f886: 7f 40 0a 00 mov.b #10, r15 ;#0x000a
f88a: b0 12 d6 f8 call #0xf8d6
uart_putc('\r');
f88e: 7f 40 0d 00 mov.b #13, r15 ;#0x000d
f892: b0 12 d6 f8 call #0xf8d6
f896: df 3f jmp $-64 ;abs 0xf856
0000f898 <__stop_progExec__>:
f898: 32 d0 f0 00 bis #240, r2 ;#0x00f0
f89c: fd 3f jmp $-4 ;abs 0xf898
0000f89e <__ctors_end>:
f89e: 30 40 30 fa br #0xfa30
0000f8a2 <uart_init>:
static volatile bool is_receiving = false;
static volatile bool has_received = false;
void uart_init(void) {
P1SEL |= TXD;
f8a2: e2 d3 26 00 bis.b #2, &0x0026 ;r3 As==10
P1DIR |= TXD;
f8a6: e2 d3 22 00 bis.b #2, &0x0022 ;r3 As==10
P1IES |= RXD; // RXD Hi/lo edge interrupt
f8aa: e2 d2 24 00 bis.b #4, &0x0024 ;r2 As==10
P1IFG &= ~RXD; // Clear RXD (flag) before enabling interrupt
f8ae: f2 f0 fb ff and.b #-5, &0x0023 ;#0xfffb
f8b2: 23 00
P1IE |= RXD; // Enable RXD interrupt
f8b4: e2 d2 25 00 bis.b #4, &0x0025 ;r2 As==10
}
f8b8: 30 41 ret
0000f8ba <uart_getc>:
bool uart_getc(uint8_t *c) {
if (!has_received) {
f8ba: 5e 42 06 02 mov.b &0x0206,r14
f8be: 4e 93 tst.b r14
f8c0: 08 24 jz $+18 ;abs 0xf8d2
return false;
}
*c = rx_byte;
f8c2: 1e 42 04 02 mov &0x0204,r14
f8c6: cf 4e 00 00 mov.b r14, 0(r15) ;0x0000(r15)
has_received = false;
f8ca: c2 43 06 02 mov.b #0, &0x0206 ;r3 As==00
return true;
f8ce: 5f 43 mov.b #1, r15 ;r3 As==01
f8d0: 30 41 ret
P1IE |= RXD; // Enable RXD interrupt
}
bool uart_getc(uint8_t *c) {
if (!has_received) {
return false;
f8d2: 4f 4e mov.b r14, r15
*c = rx_byte;
has_received = false;
return true;
}
f8d4: 30 41 ret
0000f8d6 <uart_putc>:
void uart_putc(uint8_t c) {
tx_byte = c;
f8d6: 4f 4f mov.b r15, r15
f8d8: 82 4f 02 02 mov r15, &0x0202
while(is_receiving); // Wait for RX completion
f8dc: c2 93 00 02 tst.b &0x0200
f8e0: fd 23 jnz $-4 ;abs 0xf8dc
CCTL0 = OUT; // TXD Idle as Mark
f8e2: a2 42 62 01 mov #4, &0x0162 ;r2 As==10
TACTL = TASSEL_2 + MC_2; // SMCLK, continuous mode
f8e6: b2 40 20 02 mov #544, &0x0160 ;#0x0220
f8ea: 60 01
bit_count = 0xA; // Load Bit counter, 8 bits + ST/SP
f8ec: f2 40 0a 00 mov.b #10, &0x0201 ;#0x000a
f8f0: 01 02
CCR0 = TAR; // Initialize compare register
f8f2: 92 42 70 01 mov &0x0170,&0x0172
f8f6: 72 01
CCR0 += BIT_TIME; // Set time till first bit
f8f8: b2 50 68 00 add #104, &0x0172 ;#0x0068
f8fc: 72 01
tx_byte |= 0x100; // Add stop bit to tx_byte (which is logical 1)
f8fe: b2 d0 00 01 bis #256, &0x0202 ;#0x0100
f902: 02 02
tx_byte = tx_byte << 1; // Add start bit (which is logical 0)
f904: 92 52 02 02 rla &0x0202
f908: 02 02
CCTL0 = CCIS_0 + OUTMOD_0 + CCIE + OUT;// Set signal, intial val, enable interrupts
f90a: b2 40 14 00 mov #20, &0x0162 ;#0x0014
f90e: 62 01
while ( CCTL0 & CCIE ); // Wait for previous TX completion
f910: b2 b0 10 00 bit #16, &0x0162 ;#0x0010
f914: 62 01
f916: fc 23 jnz $-6 ;abs 0xf910
}
f918: 30 41 ret
0000f91a <uart_puts>:
void uart_puts(const char *str)
{
f91a: 0b 12 push r11
f91c: 0b 4f mov r15, r11
if(*str != 0) uart_putc(*str++);
f91e: 6f 4f mov.b @r15, r15
f920: 4f 93 tst.b r15
f922: 03 24 jz $+8 ;abs 0xf92a
while(*str != 0) uart_putc(*str++);
f924: 1b 53 inc r11
f926: b0 12 d6 f8 call #0xf8d6
f92a: 6f 4b mov.b @r11, r15
f92c: 4f 93 tst.b r15
f92e: fa 23 jnz $-10 ;abs 0xf924
}
f930: 3b 41 pop r11
f932: 30 41 ret
0000f934 <port1_isr>:
/* ISR for RXD */
void port1_isr(void) __attribute__((interrupt (PORT1_VECTOR)));
void port1_isr(void) {
is_receiving = true;
f934: d2 43 00 02 mov.b #1, &0x0200 ;r3 As==01
P1IE &= ~RXD; // Disable RXD interrupt
f938: f2 f0 fb ff and.b #-5, &0x0025 ;#0xfffb
f93c: 25 00
P1IFG &= ~RXD; // Clear RXD IFG (interrupt flag)
f93e: f2 f0 fb ff and.b #-5, &0x0023 ;#0xfffb
f942: 23 00
TACTL = TASSEL_2 + MC_2; // SMCLK, continuous mode
f944: b2 40 20 02 mov #544, &0x0160 ;#0x0220
f948: 60 01
CCR0 = TAR; // Initialize compare register
f94a: 92 42 70 01 mov &0x0170,&0x0172
f94e: 72 01
CCR0 += HALF_BIT_TIME; // Set time till first bit
f950: b2 50 34 00 add #52, &0x0172 ;#0x0034
f954: 72 01
CCTL0 = OUTMOD_1 + CCIE; // Disable TX and enable interrupts
f956: b2 40 30 00 mov #48, &0x0162 ;#0x0030
f95a: 62 01
rx_byte = 0; // Initialize rx_byte
f95c: 82 43 04 02 mov #0, &0x0204 ;r3 As==00
bit_count = 9; // Load Bit counter, 8 bits + start bit
f960: f2 40 09 00 mov.b #9, &0x0201 ;#0x0009
f964: 01 02
}
f966: 00 13 reti
0000f968 <timera0_isr>:
/* ISR for TXD and RXD */
void timera0_isr(void) __attribute__((interrupt (TIMERA0_VECTOR)));
void timera0_isr(void) {
f968: 0f 12 push r15
if(!is_receiving) {
f96a: 5f 42 00 02 mov.b &0x0200,r15
f96e: 4f 93 tst.b r15
f970: 23 20 jnz $+72 ;abs 0xf9b8
CCR0 += BIT_TIME; // Add Offset to CCR0
f972: b2 50 68 00 add #104, &0x0172 ;#0x0068
f976: 72 01
if ( bit_count == 0) { // If all bits TXed
f978: c2 9f 01 02 cmp.b r15, &0x0201
f97c: 07 20 jnz $+16 ;abs 0xf98c
TACTL = TASSEL_2; // SMCLK, timer off (for power consumption)
f97e: b2 40 00 02 mov #512, &0x0160 ;#0x0200
f982: 60 01
CCTL0 &= ~ CCIE ; // Disable interrupt
f984: b2 f0 ef ff and #-17, &0x0162 ;#0xffef
f988: 62 01
f98a: 46 3c jmp $+142 ;abs 0xfa18
} else {
if (tx_byte & 0x01) {
f98c: 92 b3 02 02 bit #1, &0x0202 ;r3 As==01
f990: 07 24 jz $+16 ;abs 0xf9a0
CCTL0 = ((CCTL0 & ~OUTMOD_7 ) | OUTMOD_1); //OUTMOD_7 defines the 'window' of the field.
f992: 1f 42 62 01 mov &0x0162,r15
f996: 3f f0 1f ff and #-225, r15 ;#0xff1f
f99a: 3f d0 20 00 bis #32, r15 ;#0x0020
f99e: 06 3c jmp $+14 ;abs 0xf9ac
} else {
CCTL0 = ((CCTL0 & ~OUTMOD_7 ) | OUTMOD_5); //OUTMOD_7 defines the 'window' of the field.
f9a0: 1f 42 62 01 mov &0x0162,r15
f9a4: 3f f0 1f ff and #-225, r15 ;#0xff1f
f9a8: 3f d0 a0 00 bis #160, r15 ;#0x00a0
f9ac: 82 4f 62 01 mov r15, &0x0162
}
tx_byte = tx_byte >> 1;
f9b0: 12 c3 clrc
f9b2: 12 10 02 02 rrc &0x0202
f9b6: 2e 3c jmp $+94 ;abs 0xfa14
bit_count --;
}
} else {
CCR0 += BIT_TIME; // Add Offset to CCR0
f9b8: b2 50 68 00 add #104, &0x0172 ;#0x0068
f9bc: 72 01
if ( bit_count == 0) {
f9be: 5f 42 01 02 mov.b &0x0201,r15
f9c2: 4f 93 tst.b r15
f9c4: 1d 20 jnz $+60 ;abs 0xfa00
TACTL = TASSEL_2; // SMCLK, timer off (for power consumption)
f9c6: b2 40 00 02 mov #512, &0x0160 ;#0x0200
f9ca: 60 01
CCTL0 &= ~ CCIE ; // Disable interrupt
f9cc: b2 f0 ef ff and #-17, &0x0162 ;#0xffef
f9d0: 62 01
is_receiving = false;
f9d2: c2 4f 00 02 mov.b r15, &0x0200
P1IFG &= ~RXD; // clear RXD IFG (interrupt flag)
f9d6: f2 f0 fb ff and.b #-5, &0x0023 ;#0xfffb
f9da: 23 00
P1IE |= RXD; // enabled RXD interrupt
f9dc: e2 d2 25 00 bis.b #4, &0x0025 ;r2 As==10
if ( (rx_byte & 0x201) == 0x200) { // Validate the start and stop bits are correct
f9e0: 1f 42 04 02 mov &0x0204,r15
f9e4: 3f f0 01 02 and #513, r15 ;#0x0201
f9e8: 3f 90 00 02 cmp #512, r15 ;#0x0200
f9ec: 15 20 jnz $+44 ;abs 0xfa18
rx_byte = rx_byte >> 1; // Remove start bit
f9ee: 12 c3 clrc
f9f0: 12 10 04 02 rrc &0x0204
rx_byte &= 0xFF; // Remove stop bit
f9f4: b2 f0 ff 00 and #255, &0x0204 ;#0x00ff
f9f8: 04 02
has_received = true;
f9fa: d2 43 06 02 mov.b #1, &0x0206 ;r3 As==01
f9fe: 0c 3c jmp $+26 ;abs 0xfa18
}
} else {
if ( (P1IN & RXD) == RXD) { // If bit is set?
fa00: 5f 42 20 00 mov.b &0x0020,r15
fa04: 2f f2 and #4, r15 ;r2 As==10
fa06: 03 24 jz $+8 ;abs 0xfa0e
rx_byte |= 0x400; // Set the value in the rx_byte
fa08: b2 d0 00 04 bis #1024, &0x0204 ;#0x0400
fa0c: 04 02
}
rx_byte = rx_byte >> 1; // Shift the bits down
fa0e: 12 c3 clrc
fa10: 12 10 04 02 rrc &0x0204
bit_count --;
fa14: f2 53 01 02 add.b #-1, &0x0201 ;r3 As==11
}
}
}
fa18: 3f 41 pop r15
fa1a: 00 13 reti
0000fa1c <candle_init>:
void candle_init() {
CANDLE_DIR |= CANDLE;
fa1c: d2 d3 22 00 bis.b #1, &0x0022 ;r3 As==01
CANDLE_OUT &= ~CANDLE;
fa20: f2 f0 fe ff and.b #-2, &0x0021 ;#0xfffe
fa24: 21 00
}
fa26: 30 41 ret
fa28: 6f 6e addc.b @r14, r15
fa2a: 00 6f addc r15, r0
fa2c: 66 66 addc.b @r6, r6
...
0000fa30 <_unexpected_>:
fa30: 00 13 reti
Disassembly of section .bss:
00000200 <__bss_start>:
...
00000201 <bit_count>:
...
00000202 <tx_byte>:
...
00000204 <rx_byte>:
...
00000206 <has_received>:
...
Disassembly of section .vectors:
0000ffe0 <__ivtbl_16>:
ffe0: 9e f8 9e f8 and -1890(r8),-1740(r14);0xf89e(r8), 0xf934(r14)
ffe4: 34 f9
ffe6: 9e f8 9e f8 and -1890(r8),-1890(r14);0xf89e(r8), 0xf89e(r14)
ffea: 9e f8
ffec: 9e f8 9e f8 and -1890(r8),-1890(r14);0xf89e(r8), 0xf89e(r14)
fff0: 9e f8
fff2: 68 f9 and.b @r9, r8
fff4: 9e f8 9e f8 and -1890(r8),-1890(r14);0xf89e(r8), 0xf89e(r14)
fff8: 9e f8
fffa: 9e f8 9e f8 and -1890(r8),-2048(r14);0xf89e(r8), 0xf800(r14)
fffe: 00 f8
Disassembly of section .debug_aranges:
00000000 <.debug_aranges>:
0: 14 00 .word 0x0014; ????
2: 00 00 .word 0x0000; ????
4: 02 00 .word 0x0002; ????
6: 00 00 .word 0x0000; ????
8: 00 00 .word 0x0000; ????
a: 02 00 .word 0x0002; ????
c: a2 f8 8d 01 and @r8, &0x018d
10: 38 f8 and @r8+, r8
12: 60 00 .word 0x0060; ????
14: 00 00 .word 0x0000; ????
...
Disassembly of section .debug_pubnames:
00000000 <.debug_pubnames>:
0: 7d 00 .word 0x007d; ????
2: 00 00 .word 0x0000; ????
4: 02 00 .word 0x0002; ????
6: 00 00 .word 0x0000; ????
8: 00 00 .word 0x0000; ????
a: fd 03 .word 0x03fd; ????
c: 00 00 .word 0x0000; ????
e: 68 00 .word 0x0068; ????
10: 00 00 .word 0x0000; ????
12: 75 61 addc.b @r1+, r5
14: 72 74 subc.b @r4+, r2
16: 5f 69 6e 69 addc.b 26990(r9),r15 ;0x696e(r9)
1a: 74 00 .word 0x0074; ????
1c: 78 00 .word 0x0078; ????
1e: 00 00 .word 0x0000; ????
20: 75 61 addc.b @r1+, r5
22: 72 74 subc.b @r4+, r2
24: 5f 67 65 74 addc.b 29797(r7),r15 ;0x7465(r7)
28: 63 00 .word 0x0063; ????
2a: ab 00 .word 0x00ab; ????
2c: 00 00 .word 0x0000; ????
2e: 75 61 addc.b @r1+, r5
30: 72 74 subc.b @r4+, r2
32: 5f 70 75 74 subc.b 0x7475, r15 ;PC rel. 0x074ab
36: 63 00 .word 0x0063; ????
38: cb 00 .word 0x00cb; ????
3a: 00 00 .word 0x0000; ????
3c: 75 61 addc.b @r1+, r5
3e: 72 74 subc.b @r4+, r2
40: 5f 70 75 74 subc.b 0x7475, r15 ;PC rel. 0x074b9
44: 73 00 .word 0x0073; ????
46: 02 01 .word 0x0102; ????
48: 00 00 .word 0x0000; ????
4a: 70 6f addc.b @r15+, r0
4c: 72 74 subc.b @r4+, r2
4e: 31 5f add @r15+, r1
50: 69 73 subc.b #2, r9 ;r3 As==10
52: 72 00 .word 0x0072; ????
54: 12 01 .word 0x0112; ????
56: 00 00 .word 0x0000; ????
58: 74 69 addc.b @r9+, r4
5a: 6d 65 addc.b @r5, r13
5c: 72 61 addc.b @r1+, r2
5e: 30 5f add @r15+, r0
60: 69 73 subc.b #2, r9 ;r3 As==10
62: 72 00 .word 0x0072; ????
64: 23 01 .word 0x0123; ????
66: 00 00 .word 0x0000; ????
68: 63 61 .word 0x6163; ???? Illegal as 2-op instr
6a: 6e 64 addc.b @r4, r14
6c: 6c 65 addc.b @r5, r12
6e: 5f 69 6e 69 addc.b 26990(r9),r15 ;0x696e(r9)
72: 74 00 .word 0x0074; ????
74: 32 01 .word 0x0132; ????
76: 00 00 .word 0x0000; ????
78: 6d 61 addc.b @r1, r13
7a: 69 6e addc.b @r14, r9
7c: 00 00 .word 0x0000; ????
7e: 00 00 .word 0x0000; ????
...
Disassembly of section .debug_info:
00000000 <.debug_info>:
0: f9 03 .word 0x03f9; ????
2: 00 00 .word 0x0000; ????
4: 02 00 .word 0x0002; ????
6: 00 00 .word 0x0000; ????
8: 00 00 .word 0x0000; ????
a: 02 01 .word 0x0102; ????
c: 4d 01 .word 0x014d; ????
e: 00 00 .word 0x0000; ????
10: 01 22 jnz $-1020 ;abs 0xfc14
12: 01 00 .word 0x0001; ????
14: 00 9f cmp r15, r0
...
22: 00 00 .word 0x0000; ????
24: 00 02 .word 0x0200; ????
26: 01 06 .word 0x0601; ????
28: c7 00 .word 0x00c7; ????
2a: 00 00 .word 0x0000; ????
2c: 03 02 .word 0x0203; ????
2e: 05 69 addc r9, r5
30: 6e 74 subc.b @r4, r14
32: 00 02 .word 0x0200; ????
34: 04 05 .word 0x0504; ????
36: 6b 00 .word 0x006b; ????
38: 00 00 .word 0x0000; ????
3a: 02 08 .word 0x0802; ????
3c: 05 66 addc r6, r5
3e: 00 00 .word 0x0000; ????
40: 00 04 .word 0x0400; ????
42: 24 00 .word 0x0024; ????
44: 00 00 .word 0x0000; ????
46: 03 2b jnc $-504 ;abs 0xfe4e
48: 4c 00 .word 0x004c; ????
4a: 00 00 .word 0x0000; ????
4c: 02 01 .word 0x0102; ????
4e: 08 c5 bic r5, r8
50: 00 00 .word 0x0000; ????
52: 00 02 .word 0x0200; ????
54: 02 07 .word 0x0702; ????
56: dd 00 .word 0x00dd; ????
58: 00 00 .word 0x0000; ????
5a: 02 04 .word 0x0402; ????
5c: 07 d8 bis r8, r7
5e: 00 00 .word 0x0000; ????
60: 00 02 .word 0x0200; ????
62: 08 07 .word 0x0708; ????
64: d3 00 .word 0x00d3; ????
66: 00 00 .word 0x0000; ????
68: 05 01 .word 0x0105; ????
6a: 00 00 .word 0x0000; ????
6c: 00 00 .word 0x0000; ????
6e: 01 2e jc $-1020 ;abs 0xfc72
70: 01 a2 dadd r2, r1
72: f8 ba f8 02 bit.b @r10+, 760(r8) ;0x02f8(r8)
76: 71 02 .word 0x0271; ????
78: 06 01 .word 0x0106; ????
7a: 7d 00 .word 0x007d; ????
7c: 00 00 .word 0x0000; ????
7e: 01 37 jge $-508 ;abs 0xfe82
80: 01 9e cmp r14, r1
82: 00 00 .word 0x0000; ????
84: 00 ba bit r10, r0
86: f8 d6 f8 02 bis.b @r6+, 760(r8) ;0x02f8(r8)
8a: 71 02 .word 0x0271; ????
8c: 9e 00 .word 0x009e; ????
8e: 00 00 .word 0x0000; ????
90: 07 63 adc r7
92: 00 01 .word 0x0100; ????
94: 37 a5 dadd @r5+, r7
...
9e: 02 01 .word 0x0102; ????
a0: 02 0a .word 0x0a02; ????
a2: 01 00 .word 0x0001; ????
a4: 00 08 .word 0x0800; ????
a6: 02 41 mov r1, r2
a8: 00 00 .word 0x0000; ????
aa: 00 09 .word 0x0900; ????
ac: 01 6b addc r11, r1
ae: 01 00 .word 0x0001; ????
b0: 00 01 .word 0x0100; ????
b2: 42 01 .word 0x0142; ????
b4: d6 f8 1a f9 and.b -1766(r8),28930(r6);0xf91a(r8), 0x7102(r6)
b8: 02 71
ba: 02 cb bic r11, r2
bc: 00 00 .word 0x0000; ????
be: 00 0a .word 0x0a00; ????
c0: 63 00 .word 0x0063; ????
c2: 01 42 mov r2, r1
c4: 41 00 .word 0x0041; ????
c6: 00 00 .word 0x0000; ????
c8: 01 5f add r15, r1
ca: 00 0b .word 0x0b00; ????
cc: 01 81 sub r1, r1
ce: 01 00 .word 0x0001; ????
d0: 00 01 .word 0x0100; ????
d2: 56 01 .word 0x0156; ????
d4: 1a f9 34 f9 and -1740(r9),r10 ;0xf934(r9)
d8: 12 00 .word 0x0012; ????
da: 00 00 .word 0x0000; ????
dc: f0 00 .word 0x00f0; ????
de: 00 00 .word 0x0000; ????
e0: 07 73 sbc r7
e2: 74 72 subc.b #8, r4 ;r2 As==11
e4: 00 01 .word 0x0100; ????
e6: 56 f0 00 00 and.b 0x0000, r6 ;PC rel. 0x000ea
ea: 00 26 jz $-1022 ;abs 0xfcec
ec: 00 00 .word 0x0000; ????
ee: 00 00 .word 0x0000; ????
f0: 08 02 .word 0x0208; ????
f2: f6 00 .word 0x00f6; ????
f4: 00 00 .word 0x0000; ????
f6: 0c fb and r11, r12
f8: 00 00 .word 0x0000; ????
fa: 00 02 .word 0x0200; ????
fc: 01 06 .word 0x0601; ????
fe: ce 00 .word 0x00ce; ????
100: 00 00 .word 0x0000; ????
102: 05 01 .word 0x0105; ????
104: f3 00 .word 0x00f3; ????
106: 00 00 .word 0x0000; ????
108: 01 5e add r14, r1
10a: 01 34 jge $+4 ;abs 0x10e
10c: f9 68 f9 02 addc.b @r8+, 761(r9) ;0x02f9(r9)
110: 71 02 .word 0x0271; ????
112: 0d 01 .word 0x010d; ????
114: 75 01 .word 0x0175; ????
116: 00 00 .word 0x0000; ????
118: 01 6f addc r15, r1
11a: 01 68 addc r8, r1
11c: f9 1c .word 0x1cf9; ????
11e: fa 3f jmp $-10 ;abs 0x114
120: 00 00 .word 0x0000; ????
122: 00 0e .word 0x0e00; ????
124: 01 0a .word 0x0a01; ????
126: 00 00 .word 0x0000; ????
128: 00 01 .word 0x0100; ????
12a: 9c 1c .word 0x1c9c; ????
12c: fa 28 jnc $+502 ;abs 0x322
12e: fa 02 .word 0x02fa; ????
130: 71 02 .word 0x0271; ????
132: 0f 01 .word 0x010f; ????
134: 1f 00 .word 0x001f; ????
136: 00 00 .word 0x0000; ????
138: 01 a1 dadd r1, r1
13a: 01 2c jc $+4 ;abs 0x13e
13c: 00 00 .word 0x0000; ????
13e: 00 38 jl $+2 ;abs 0x140
140: f8 98 f8 53 cmp.b @r8+, 21496(r8);0x53f8(r8)
144: 00 00 .word 0x0000; ????
146: 00 58 add r8, r0
148: 01 00 .word 0x0001; ????
14a: 00 10 rrc r0
14c: 63 00 .word 0x0063; ????
14e: 01 ab dadd r11, r1
150: 41 00 .word 0x0041; ????
152: 00 00 .word 0x0000; ????
154: 02 91 cmp r1, r2
156: 7c 00 .word 0x007c; ????
158: 11 46 01 00 mov 1(r6), r1 ;0x0001(r6)
15c: 00 02 .word 0x0200; ????
15e: 0f 01 .word 0x010f; ????
160: 43 01 .word 0x0143; ????
162: 00 00 .word 0x0000; ????
164: 6a 01 .word 0x016a; ????
166: 00 00 .word 0x0000; ????
168: 01 01 .word 0x0101; ????
16a: 12 4c 00 00 mov 0(r12), r2 ;0x0000(r12)
16e: 00 11 rra r0
170: 3e 00 .word 0x003e; ????
172: 00 00 .word 0x0000; ????
174: 02 11 rra r2
176: 01 3b jl $-508 ;abs 0xff7a
178: 00 00 .word 0x0000; ????
17a: 00 6a addc r10, r0
17c: 01 00 .word 0x0001; ????
17e: 00 01 .word 0x0100; ????
180: 01 11 rra r1
182: 66 01 .word 0x0166; ????
184: 00 00 .word 0x0000; ????
186: 02 97 cmp r7, r2
188: 01 63 adc r1
18a: 01 00 .word 0x0001; ????
18c: 00 93 tst r0
18e: 01 00 .word 0x0001; ????
190: 00 01 .word 0x0100; ????
192: 01 0c .word 0x0c01; ????
194: 6a 01 .word 0x016a; ????
196: 00 00 .word 0x0000; ????
198: 11 19 .word 0x1911; ????
19a: 00 00 .word 0x0000; ????
19c: 00 02 .word 0x0200; ????
19e: 99 01 .word 0x0199; ????
1a0: 16 00 .word 0x0016; ????
1a2: 00 00 .word 0x0000; ????
1a4: 6a 01 .word 0x016a; ????
1a6: 00 00 .word 0x0000; ????
1a8: 01 01 .word 0x0101; ????
1aa: 11 8e 01 00 sub 1(r14), r1 ;0x0001(r14)
1ae: 00 02 .word 0x0200; ????
1b0: 9b 01 .word 0x019b; ????
1b2: 8b 01 .word 0x018b; ????
1b4: 00 00 .word 0x0000; ????
1b6: 6a 01 .word 0x016a; ????
1b8: 00 00 .word 0x0000; ????
1ba: 01 01 .word 0x0101; ????
1bc: 11 35 jge $+548 ;abs 0x3e0
1be: 01 00 .word 0x0001; ????
1c0: 00 02 .word 0x0200; ????
1c2: 9d 01 .word 0x019d; ????
1c4: 32 01 .word 0x0132; ????
1c6: 00 00 .word 0x0000; ????
1c8: 6a 01 .word 0x016a; ????
1ca: 00 00 .word 0x0000; ????
1cc: 01 01 .word 0x0101; ????
1ce: 11 ed 00 00 xor 0(r13), r1 ;0x0000(r13)
1d2: 00 02 .word 0x0200; ????
1d4: 9f 01 .word 0x019f; ????
1d6: ea 00 .word 0x00ea; ????
1d8: 00 00 .word 0x0000; ????
1da: 6a 01 .word 0x016a; ????
1dc: 00 00 .word 0x0000; ????
1de: 01 01 .word 0x0101; ????
1e0: 11 3e jmp $-988 ;abs 0xfe04
1e2: 01 00 .word 0x0001; ????
1e4: 00 02 .word 0x0200; ????
1e6: a1 01 .word 0x01a1; ????
1e8: 3b 01 .word 0x013b; ????
1ea: 00 00 .word 0x0000; ????
1ec: 6a 01 .word 0x016a; ????
1ee: 00 00 .word 0x0000; ????
1f0: 01 01 .word 0x0101; ????
1f2: 11 77 00 00 subc 0(r7), r1 ;0x0000(r7)
1f6: 00 02 .word 0x0200; ????
1f8: a3 01 .word 0x01a3; ????
1fa: 74 00 .word 0x0074; ????
1fc: 00 00 .word 0x0000; ????
1fe: 6a 01 .word 0x016a; ????
200: 00 00 .word 0x0000; ????
202: 01 01 .word 0x0101; ????
204: 11 2c jc $+36 ;abs 0x228
206: 01 00 .word 0x0001; ????
208: 00 02 .word 0x0200; ????
20a: c0 01 .word 0x01c0; ????
20c: 29 01 .word 0x0129; ????
20e: 00 00 .word 0x0000; ????
210: 16 02 .word 0x0216; ????
212: 00 00 .word 0x0000; ????
214: 01 01 .word 0x0101; ????
216: 12 53 inc r2
218: 00 00 .word 0x0000; ????
21a: 00 11 rra r0
21c: 8a 00 .word 0x008a; ????
21e: 00 00 .word 0x0000; ????
220: 02 c2 bic r2, r2
222: 01 87 sub r7, r1
224: 00 00 .word 0x0000; ????
226: 00 16 .word 0x1600; ????
228: 02 00 .word 0x0002; ????
22a: 00 01 .word 0x0100; ????
22c: 01 13 reti ;return from interupt
22e: 54 41 52 00 mov.b 82(r1), r4 ;0x0052(r1)
232: 02 c6 bic r6, r2
234: 01 50 add r0, r1
236: 00 00 .word 0x0000; ????
238: 00 16 .word 0x1600; ????
23a: 02 00 .word 0x0002; ????
23c: 00 01 .word 0x0100; ????
23e: 01 11 rra r1
240: 1b 01 .word 0x011b; ????
242: 00 00 .word 0x0000; ????
244: 02 c8 bic r8, r2
246: 01 18 .word 0x1801; ????
248: 01 00 .word 0x0001; ????
24a: 00 16 .word 0x1600; ????
24c: 02 00 .word 0x0002; ????
24e: 00 01 .word 0x0100; ????
250: 01 11 rra r1
252: 5c 01 .word 0x015c; ????
254: 00 00 .word 0x0000; ????
256: 02 69 addc r9, r2
258: 02 59 add r9, r2
25a: 01 00 .word 0x0001; ????
25c: 00 16 .word 0x1600; ????
25e: 02 00 .word 0x0002; ????
260: 00 01 .word 0x0100; ????
262: 01 11 rra r1
264: 2f 00 .word 0x002f; ????
266: 00 00 .word 0x0000; ????
268: 02 99 cmp r9, r2
26a: 02 2c jc $+6 ;abs 0x270
26c: 00 00 .word 0x0000; ????
26e: 00 93 tst r0
270: 01 00 .word 0x0001; ????
272: 00 01 .word 0x0100; ????
274: 01 11 rra r1
276: 5a 00 .word 0x005a; ????
278: 00 00 .word 0x0000; ????
27a: 02 9b cmp r11, r2
27c: 02 57 add r7, r2
27e: 00 00 .word 0x0000; ????
280: 00 93 tst r0
282: 01 00 .word 0x0001; ????
284: 00 01 .word 0x0100; ????
286: 01 14 .word 0x1401; ????
288: 46 00 .word 0x0046; ????
28a: 00 00 .word 0x0000; ????
28c: 01 24 jz $+4 ;abs 0x290
28e: 96 02 .word 0x0296; ????
290: 00 00 .word 0x0000; ????
292: 03 03 .word 0x0303; ????
294: 01 02 .word 0x0201; ????
296: 12 41 00 00 mov 0(r1), r2 ;0x0000(r1)
29a: 00 14 .word 0x1400; ????
29c: 10 01 .word 0x0110; ????
29e: 00 00 .word 0x0000; ????
2a0: 01 26 jz $-1020 ;abs 0xfea4
2a2: 16 02 .word 0x0216; ????
2a4: 00 00 .word 0x0000; ????
2a6: 03 03 .word 0x0303; ????
2a8: 02 02 .word 0x0202; ????
2aa: 14 94 01 00 cmp 1(r4), r4 ;0x0001(r4)
2ae: 00 01 .word 0x0100; ????
2b0: 28 16 .word 0x1628; ????
2b2: 02 00 .word 0x0002; ????
2b4: 00 03 .word 0x0300; ????
2b6: 03 04 .word 0x0403; ????
2b8: 02 14 .word 0x1402; ????
2ba: 92 00 .word 0x0092; ????
2bc: 00 00 .word 0x0000; ????
2be: 01 2a jnc $-1020 ;abs 0xfec2
2c0: c8 02 .word 0x02c8; ????
2c2: 00 00 .word 0x0000; ????
2c4: 03 03 .word 0x0303; ????
2c6: 00 02 .word 0x0200; ????
2c8: 12 9e 00 00 cmp 0(r14), r2 ;0x0000(r14)
2cc: 00 14 .word 0x1400; ????
2ce: fd 00 .word 0x00fd; ????
2d0: 00 00 .word 0x0000; ????
2d2: 01 2c jc $+4 ;abs 0x2d6
2d4: c8 02 .word 0x02c8; ????
2d6: 00 00 .word 0x0000; ????
2d8: 03 03 .word 0x0303; ????
2da: 06 02 .word 0x0206; ????
2dc: 11 46 01 00 mov 1(r6), r1 ;0x0001(r6)
2e0: 00 02 .word 0x0200; ????
2e2: 0f 01 .word 0x010f; ????
2e4: 43 01 .word 0x0143; ????
2e6: 00 00 .word 0x0000; ????
2e8: 6a 01 .word 0x016a; ????
2ea: 00 00 .word 0x0000; ????
2ec: 01 01 .word 0x0101; ????
2ee: 11 3e jmp $-988 ;abs 0xff12
2f0: 00 00 .word 0x0000; ????
2f2: 00 02 .word 0x0200; ????
2f4: 11 01 .word 0x0111; ????
2f6: 3b 00 .word 0x003b; ????
2f8: 00 00 .word 0x0000; ????
2fa: 6a 01 .word 0x016a; ????
2fc: 00 00 .word 0x0000; ????
2fe: 01 01 .word 0x0101; ????
300: 11 66 01 00 addc 1(r6), r1 ;0x0001(r6)
304: 00 02 .word 0x0200; ????
306: 97 01 .word 0x0197; ????
308: 63 01 .word 0x0163; ????
30a: 00 00 .word 0x0000; ????
30c: 93 01 .word 0x0193; ????
30e: 00 00 .word 0x0000; ????
310: 01 01 .word 0x0101; ????
312: 11 19 .word 0x1911; ????
314: 00 00 .word 0x0000; ????
316: 00 02 .word 0x0200; ????
318: 99 01 .word 0x0199; ????
31a: 16 00 .word 0x0016; ????
31c: 00 00 .word 0x0000; ????
31e: 6a 01 .word 0x016a; ????
320: 00 00 .word 0x0000; ????
322: 01 01 .word 0x0101; ????
324: 11 8e 01 00 sub 1(r14), r1 ;0x0001(r14)
328: 00 02 .word 0x0200; ????
32a: 9b 01 .word 0x019b; ????
32c: 8b 01 .word 0x018b; ????
32e: 00 00 .word 0x0000; ????
330: 6a 01 .word 0x016a; ????
332: 00 00 .word 0x0000; ????
334: 01 01 .word 0x0101; ????
336: 11 35 jge $+548 ;abs 0x55a
338: 01 00 .word 0x0001; ????
33a: 00 02 .word 0x0200; ????
33c: 9d 01 .word 0x019d; ????
33e: 32 01 .word 0x0132; ????
340: 00 00 .word 0x0000; ????
342: 6a 01 .word 0x016a; ????
344: 00 00 .word 0x0000; ????
346: 01 01 .word 0x0101; ????
348: 11 ed 00 00 xor 0(r13), r1 ;0x0000(r13)
34c: 00 02 .word 0x0200; ????
34e: 9f 01 .word 0x019f; ????
350: ea 00 .word 0x00ea; ????
352: 00 00 .word 0x0000; ????
354: 6a 01 .word 0x016a; ????
356: 00 00 .word 0x0000; ????
358: 01 01 .word 0x0101; ????
35a: 11 3e jmp $-988 ;abs 0xff7e
35c: 01 00 .word 0x0001; ????
35e: 00 02 .word 0x0200; ????
360: a1 01 .word 0x01a1; ????
362: 3b 01 .word 0x013b; ????
364: 00 00 .word 0x0000; ????
366: 6a 01 .word 0x016a; ????
368: 00 00 .word 0x0000; ????
36a: 01 01 .word 0x0101; ????
36c: 11 77 00 00 subc 0(r7), r1 ;0x0000(r7)
370: 00 02 .word 0x0200; ????
372: a3 01 .word 0x01a3; ????
374: 74 00 .word 0x0074; ????
376: 00 00 .word 0x0000; ????
378: 6a 01 .word 0x016a; ????
37a: 00 00 .word 0x0000; ????
37c: 01 01 .word 0x0101; ????
37e: 11 2c jc $+36 ;abs 0x3a2
380: 01 00 .word 0x0001; ????
382: 00 02 .word 0x0200; ????
384: c0 01 .word 0x01c0; ????
386: 29 01 .word 0x0129; ????
388: 00 00 .word 0x0000; ????
38a: 16 02 .word 0x0216; ????
38c: 00 00 .word 0x0000; ????
38e: 01 01 .word 0x0101; ????
390: 11 8a 00 00 sub 0(r10), r1 ;0x0000(r10)
394: 00 02 .word 0x0200; ????
396: c2 01 .word 0x01c2; ????
398: 87 00 .word 0x0087; ????
39a: 00 00 .word 0x0000; ????
39c: 16 02 .word 0x0216; ????
39e: 00 00 .word 0x0000; ????
3a0: 01 01 .word 0x0101; ????
3a2: 13 54 .word 0x5413; ???? Illegal as 2-op instr
3a4: 41 52 add.b r2, r1
3a6: 00 02 .word 0x0200; ????
3a8: c6 01 .word 0x01c6; ????
3aa: 50 00 .word 0x0050; ????
3ac: 00 00 .word 0x0000; ????
3ae: 16 02 .word 0x0216; ????
3b0: 00 00 .word 0x0000; ????
3b2: 01 01 .word 0x0101; ????
3b4: 11 1b .word 0x1b11; ????
3b6: 01 00 .word 0x0001; ????
3b8: 00 02 .word 0x0200; ????
3ba: c8 01 .word 0x01c8; ????
3bc: 18 01 .word 0x0118; ????
3be: 00 00 .word 0x0000; ????
3c0: 16 02 .word 0x0216; ????
3c2: 00 00 .word 0x0000; ????
3c4: 01 01 .word 0x0101; ????
3c6: 11 5c 01 00 add 1(r12), r1 ;0x0001(r12)
3ca: 00 02 .word 0x0200; ????
3cc: 69 02 .word 0x0269; ????
3ce: 59 01 .word 0x0159; ????
3d0: 00 00 .word 0x0000; ????
3d2: 16 02 .word 0x0216; ????
3d4: 00 00 .word 0x0000; ????
3d6: 01 01 .word 0x0101; ????
3d8: 11 2f jc $-476 ;abs 0x1fc
3da: 00 00 .word 0x0000; ????
3dc: 00 02 .word 0x0200; ????
3de: 99 02 .word 0x0299; ????
3e0: 2c 00 .word 0x002c; ????
3e2: 00 00 .word 0x0000; ????
3e4: 93 01 .word 0x0193; ????
3e6: 00 00 .word 0x0000; ????
3e8: 01 01 .word 0x0101; ????
3ea: 11 5a 00 00 add 0(r10), r1 ;0x0000(r10)
3ee: 00 02 .word 0x0200; ????
3f0: 9b 02 .word 0x029b; ????
3f2: 57 00 .word 0x0057; ????
3f4: 00 00 .word 0x0000; ????
3f6: 93 01 .word 0x0193; ????
3f8: 00 00 .word 0x0000; ????
3fa: 01 01 .word 0x0101; ????
...
Disassembly of section .debug_abbrev:
00000000 <.debug_abbrev>:
0: 01 11 rra r1
2: 01 25 jz $+516 ;abs 0x206
4: 0e 13 reti ;return from interupt
6: 0b 03 .word 0x030b; ????
8: 0e 1b .word 0x1b0e; ????
a: 0e 11 rra r14
c: 01 52 add r2, r1
e: 01 55 add r5, r1
10: 06 10 rrc r6
12: 06 00 .word 0x0006; ????
14: 00 02 .word 0x0200; ????
16: 24 00 .word 0x0024; ????
18: 0b 0b .word 0x0b0b; ????
1a: 3e 0b .word 0x0b3e; ????
1c: 03 0e .word 0x0e03; ????
1e: 00 00 .word 0x0000; ????
20: 03 24 jz $+8 ;abs 0x28
22: 00 0b .word 0x0b00; ????
24: 0b 3e jmp $-1000 ;abs 0xfc3c