Add top level README

Author: ultraembedded

README.md

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+### Various HDL (Verilog) IP Cores
+
+Github:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master)
+
+
+#### Catalogue
+
+| Name | Description   |
+| ---- | ------------- |
+| asram16_axi4 | AXI4 -> Async SRAM (16-bit) Interface |
+| dbg_bridge | UART -> AXI4 Debug Bridge |
+| ftdi_async_bridge | FTDI Asynchronous FIFO Interface |
+| i2s | I2S Master |
+| sdram | Simple SDRAM Controller |
+| spdif | SPDIF Transmitter |
+| spilite_axi4l | SPI-Lite SPI Master Interface |
+| uart | UART |
+| ulpi_wrapper | ULPI Link Wrapper |
+| usb_device | USB Peripheral Interface |
+| usb_host | USB 1.1 Host Controller |
+| usb_sniffer | USB Sniffer |