cpu: fix a few compiler warnings

Author: Roman Dubtsov

cmake/platform.cmake

@@ -110,10 +110,8 @@ elseif(UNIX OR MINGW)
         if(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 5.0)
             set(DEF_ARCH_OPT_FLAGS "-march=native -mtune=native")
         endif()
-        if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 6.0)
-            # suppress warning on assumptions made regarding overflow (#146)
-            append(CMAKE_CCXX_NOWARN_FLAGS "-Wno-strict-overflow")
-        endif()
+        # suppress warning on assumptions made regarding overflow (#146)
+        append(CMAKE_CCXX_NOWARN_FLAGS "-Wno-strict-overflow")
     elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Intel")
         set(DEF_ARCH_OPT_FLAGS "-xHOST")
         # workaround for Intel Compiler 16.0 that produces error caused

src/cpu/gemm/ref_gemm.cpp

@@ -138,11 +138,12 @@ void gemm_ithr(const int M, const int N, const int K, const data_t alpha,
         return;
 
     if ((K <= 0) || (alpha == static_cast<data_t>(0))) {
+        ptrdiff_t MN = (ptrdiff_t)N * M;
         if (beta == static_cast<data_t>(0.)) {
-            for (int j = 0; j < N * M; j++)
+            for (ptrdiff_t j = 0; j < MN; j++)
                 C[j] = static_cast<data_t>(0.);
         } else if (beta != static_cast<data_t>(1.)) {
-            for (int j = 0; j < N * M; j++)
+            for (ptrdiff_t j = 0; j < MN; j++)
                 C[j] *= beta;
         }
         return;

src/cpu/jit_avx512_common_conv_winograd_kernel_f32.cpp

@@ -91,8 +91,9 @@ struct prefetcher_t {
         int cache_latency;
         switch (cache_type_) {
         case L1: cache_latency = 14; break;
-        case L2: cache_latency = 250; break;
-        case L3: cache_latency = 250; break;
+        case L2:
+        case L3:
+        default: cache_latency = 250; break;
         }
 
         prefetch_distance_ = div_up(cache_latency, nb_cache_lines_to_prefetch_);

src/cpu/jit_avx512_core_u8s8s32x_wino_convolution.cpp

@@ -237,22 +237,22 @@ struct jit_avx512_core_u8s8s32x_wino_conv_dst_trans_t: public jit_generator {
     }
     Zmm vreg_stg(int id) { // 8
         const int id_reg_stg = jcp.alpha * jcp.alpha + id;
-        assert(id_reg_stg < jcp.alpha * jcp.alpha + 8);
+        assert(id < 8);
         return Zmm(31 - id_reg_stg);
     }
     Zmm vreg_out(int id) { // 4
         const int id_reg_out = jcp.alpha * jcp.alpha + 8 + id;
-        assert(id_reg_out < jcp.alpha * jcp.alpha + 12);
+        assert(id < 4);
         return Zmm(31 - id_reg_out);
     }
     Xmm xmm_out(int id) { // 4
         const int id_reg_out = jcp.alpha * jcp.alpha + 8 + id;
-        assert(id_reg_out < jcp.alpha * jcp.alpha + 12);
+        assert(id < 4);
         return Xmm(31 - id_reg_out);
     }
     Zmm vreg_tmp(int id) { // 2
         const int id_reg_tmp = jcp.alpha * jcp.alpha + 12 + id;
-        assert(id_reg_tmp < jcp.alpha * jcp.alpha + 14);
+        assert(id < 2);
         return Zmm(31 - id_reg_tmp);
     }
 

src/cpu/simple_concat.hpp

@@ -114,6 +114,7 @@ struct simple_concat_t: public cpu_primitive_t {
 private:
     static void format_perm(
             const int ndims, const stride_t *strides, int *perm, int *iperm) {
+        assert(ndims >= 0);
         bool swapped;
         strides_t strides_tmp;
         utils::array_copy(strides_tmp, strides, ndims);

tests/benchdnn/reorder/bench_reorder.cpp

@@ -67,10 +67,10 @@ void check(const prb_t *p) {
 void run() {
     for (auto &idt: v_idt)
     for (auto &odt: v_odt)
-    for (int swap_dt = 0; swap_dt < 1 + both_dir_dt * (idt != odt); ++swap_dt)
+    for (int swap_dt = 0; swap_dt < (both_dir_dt && idt != odt ? 2 : 1); ++swap_dt)
     for (auto &ifmt: v_ifmt)
     for (auto &ofmt: v_ofmt)
-    for (int swap_fmt = 0; swap_fmt < 1 + both_dir_fmt * (ifmt != ofmt); ++swap_fmt)
+    for (int swap_fmt = 0; swap_fmt < (both_dir_fmt && ifmt != ofmt ? 2 : 1); ++swap_fmt)
     for (auto &dims: v_dims)
     {
         reorder_conf_t reorder_conf{dims,