@@ -37,36 +37,44 @@ typedef int FPU_mode_type;
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#else
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typedef int64_t FPU_mode_type;
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#endif
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- #if defined(__i386__) || defined(__x86_64__) || defined(_MSC_VER) \
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- || defined(__MINGW32__)
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+ #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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+ || defined(_M_X64) || defined( __MINGW32__)
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#include < xmmintrin.h>
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+ #elif defined(_M_ARM64)
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+ #include < intrin.h>
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#elif defined(__PPC__)
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#include < fpu_control.h>
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extern __thread fpu_control_t fpu_control;
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#elif defined(__mips__)
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#include " mips/m32c1.h"
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#endif
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+
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// Set the reference hardware floating point unit to FTZ mode
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- inline void ForceFTZ (FPU_mode_type *mode )
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+ inline void ForceFTZ (FPU_mode_type *oldMode )
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{
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- #if defined(__i386__) || defined(__x86_64__) || defined(_MSC_VER) \
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- || defined (__MINGW32__)
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- *mode = _mm_getcsr ();
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- _mm_setcsr (*mode | 0x8040 );
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+ #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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+ || defined (_M_X64) || defined ( __MINGW32__)
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+ *oldMode = _mm_getcsr ();
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+ _mm_setcsr (*oldMode | 0x8040 );
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#elif defined(__PPC__)
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- *mode = fpu_control;
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+ *oldMode = fpu_control;
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fpu_control |= _FPU_MASK_NI;
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#elif defined(__arm__)
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unsigned fpscr;
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__asm__ volatile (" fmrx %0, fpscr" : " =r" (fpscr));
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- *mode = fpscr;
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+ *oldMode = fpscr;
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__asm__ volatile (" fmxr fpscr, %0" ::" r" (fpscr | (1U << 24 )));
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// Add 64 bit support
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- #elif defined(__aarch64__)
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+ #elif defined(__aarch64__) // Clang
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uint64_t fpscr;
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__asm__ volatile (" mrs %0, fpcr" : " =r" (fpscr));
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- *mode = fpscr;
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+ *oldMode = fpscr;
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__asm__ volatile (" msr fpcr, %0" ::" r" (fpscr | (1U << 24 )));
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+ #elif defined(_M_ARM64) // Visual Studio
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+ uint64_t fpscr;
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+ fpscr = _ReadStatusReg (ARM64_FPSR);
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+ *oldMode = fpscr;
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+ _WriteStatusReg (ARM64_FPCR, fpscr | (1U << 24 ));
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#elif defined(__mips__)
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fpa_bissr (FPA_CSR_FS);
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#else
@@ -75,26 +83,31 @@ inline void ForceFTZ(FPU_mode_type *mode)
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}
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// Disable the denorm flush to zero
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- inline void DisableFTZ (FPU_mode_type *mode )
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+ inline void DisableFTZ (FPU_mode_type *oldMode )
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{
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- #if defined(__i386__) || defined(__x86_64__) || defined(_MSC_VER) \
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- || defined (__MINGW32__)
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- *mode = _mm_getcsr ();
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- _mm_setcsr (*mode & ~0x8040 );
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+ #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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+ || defined (_M_X64) || defined ( __MINGW32__)
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+ *oldMode = _mm_getcsr ();
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+ _mm_setcsr (*oldMode & ~0x8040 );
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#elif defined(__PPC__)
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*mode = fpu_control;
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fpu_control &= ~_FPU_MASK_NI;
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#elif defined(__arm__)
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unsigned fpscr;
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__asm__ volatile (" fmrx %0, fpscr" : " =r" (fpscr));
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- *mode = fpscr;
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+ *oldMode = fpscr;
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__asm__ volatile (" fmxr fpscr, %0" ::" r" (fpscr & ~(1U << 24 )));
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// Add 64 bit support
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- #elif defined(__aarch64__)
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+ #elif defined(__aarch64__) // Clang
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uint64_t fpscr;
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__asm__ volatile (" mrs %0, fpcr" : " =r" (fpscr));
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- *mode = fpscr;
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+ *oldMode = fpscr;
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__asm__ volatile (" msr fpcr, %0" ::" r" (fpscr & ~(1U << 24 )));
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+ #elif defined(_M_ARM64) // Visual Studio
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+ uint64_t fpscr;
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+ fpscr = _ReadStatusReg (ARM64_FPSR);
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+ *oldMode = fpscr;
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+ _WriteStatusReg (ARM64_FPCR, fpscr & ~(1U << 24 ));
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#elif defined(__mips__)
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fpa_bicsr (FPA_CSR_FS);
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#else
@@ -105,16 +118,18 @@ inline void DisableFTZ(FPU_mode_type *mode)
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// Restore the reference hardware to floating point state indicated by *mode
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inline void RestoreFPState (FPU_mode_type *mode)
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{
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- #if defined(__i386__) || defined(__x86_64__) || defined(_MSC_VER) \
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- || defined (__MINGW32__)
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+ #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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+ || defined (_M_X64) || defined ( __MINGW32__)
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_mm_setcsr (*mode);
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#elif defined(__PPC__)
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fpu_control = *mode;
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#elif defined(__arm__)
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__asm__ volatile (" fmxr fpscr, %0" ::" r" (*mode));
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// Add 64 bit support
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- #elif defined(__aarch64__)
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+ #elif defined(__aarch64__) // Clang
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__asm__ volatile (" msr fpcr, %0" ::" r" (*mode));
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+ #elif defined(_M_ARM64) // Visual Studio
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+ _WriteStatusReg (ARM64_FPCR, *mode);
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#elif defined(__mips__)
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// Mips runs by default with DAZ=1 FTZ=1
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#else
@@ -125,4 +140,4 @@ inline void RestoreFPState(FPU_mode_type *mode)
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#error ForceFTZ and RestoreFPState need implentations
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#endif
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- #endif
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+ #endif
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