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Bump llvm to ddc8db79 (Xilinx#997)
* Bump llvm to ddc8db79 * Fixup nodiscard * Update tests after llvm bump * Bump mlir-aie version
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14 files changed

+39
-39
lines changed

14 files changed

+39
-39
lines changed

‎mlir/lib/Conversion/AIRToAIEPass.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2772,7 +2772,7 @@ class AIRToAIEPass : public air::impl::AIRToAIEBase<AIRToAIEPass> {
27722772
alloc = memcpyOpIf.getSrcMemref();
27732773
}
27742774

2775-
if (auto bco = dyn_cast<bufferization::ToMemrefOp>(alloc.getDefiningOp()))
2775+
if (auto bco = dyn_cast<bufferization::ToBufferOp>(alloc.getDefiningOp()))
27762776
builder.setInsertionPoint(bco.getOperand().getDefiningOp());
27772777
else if (isa<memref::AllocaOp>(alloc.getDefiningOp()))
27782778
builder.setInsertionPoint(alloc.getDefiningOp());

‎mlir/lib/Transform/AIRDependencyScheduleOpt.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4071,7 +4071,7 @@ class AIRFuseChannels
40714071
BackwardSliceOptions bsOptions{[&](Operation *o) {
40724072
return !isa<LoopLikeOpInterface>(o) && !isa<air::HierarchyInterface>(o);
40734073
}};
4074-
getBackwardSlice(op, &backwardSlice, bsOptions);
4074+
(void)getBackwardSlice(op, &backwardSlice, bsOptions);
40754075
for (auto b : backwardSlice)
40764076
if (air::isPure(b))
40774077
builder.clone(*b, remap);

‎mlir/lib/Transform/AIRDmaToChannel.cpp‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -599,12 +599,13 @@ LogicalResult HoistingAffineIf(affine::AffineIfOp op) {
599599
SetVector<Operation *> backwardSlice;
600600
BackwardSliceOptions bsOptions{[&](Operation *o) { return o != hier_op; }};
601601
for (auto ext_channel_op : externalGetPut) {
602-
getBackwardSlice(ext_channel_op.getOperation(), &backwardSlice, bsOptions);
602+
(void)getBackwardSlice(ext_channel_op.getOperation(), &backwardSlice,
603+
bsOptions);
603604

604605
for (auto parent = ext_channel_op->getParentOp();
605606
!isa<air::HierarchyInterface>(parent);
606607
parent = parent->getParentOp()) {
607-
getBackwardSlice(parent, &backwardSlice, bsOptions);
608+
(void)getBackwardSlice(parent, &backwardSlice, bsOptions);
608609
backwardSlice.insert(parent);
609610
}
610611
}
@@ -815,14 +816,14 @@ class AIRDmaToAIRChannelConversion
815816
BackwardSliceOptions bsOptions{
816817
[&](Operation *o) { return o != hier_op; }};
817818
for (auto ext_channel_op : externalGetPut) {
818-
getBackwardSlice(ext_channel_op.getOperation(), &backwardSlice,
819-
bsOptions);
819+
(void)getBackwardSlice(ext_channel_op.getOperation(), &backwardSlice,
820+
bsOptions);
820821
}
821822

822823
for (auto parent = op->getParentOp();
823824
!isa<air::HierarchyInterface>(parent);
824825
parent = parent->getParentOp()) {
825-
getBackwardSlice(parent, &backwardSlice, bsOptions);
826+
(void)getBackwardSlice(parent, &backwardSlice, bsOptions);
826827
backwardSlice.insert(parent);
827828
}
828829

@@ -857,7 +858,7 @@ class AIRDmaToAIRChannelConversion
857858
for (auto b : backwardSliceCopy) {
858859
if (dyn_cast<air::ExecuteOp>(b)) {
859860
for (auto &exec_child_op : b->getRegions().front().getOps()) {
860-
getBackwardSlice(&exec_child_op, &backwardSlice, bsOptions);
861+
(void)getBackwardSlice(&exec_child_op, &backwardSlice, bsOptions);
861862
backwardSlice.insert(&exec_child_op);
862863
}
863864
}
@@ -1218,7 +1219,7 @@ class AIRDemoteDmaToAIRHierarchyConversion
12181219
// Transitive defs up to scf.for.
12191220
BackwardSliceOptions bsOptions{
12201221
[&](Operation *o) { return o != hier_op && !isa<scf::ForOp>(o); }};
1221-
getBackwardSlice(op.getOperation(), &backwardSlice, bsOptions);
1222+
(void)getBackwardSlice(op.getOperation(), &backwardSlice, bsOptions);
12221223

12231224
if (hoist_herd) {
12241225
// Transitive defs up to air.herd.
@@ -1227,7 +1228,7 @@ class AIRDemoteDmaToAIRHierarchyConversion
12271228
for (auto parent = op->getParentOp();
12281229
!isa<air::HierarchyInterface>(parent);
12291230
parent = parent->getParentOp()) {
1230-
getBackwardSlice(parent, &backwardSlice, bsOptionsHoistHerd);
1231+
(void)getBackwardSlice(parent, &backwardSlice, bsOptionsHoistHerd);
12311232
backwardSlice.insert(parent);
12321233
}
12331234
} else {
@@ -1246,7 +1247,7 @@ class AIRDemoteDmaToAIRHierarchyConversion
12461247
if (!execOp)
12471248
continue;
12481249
for (auto &childOp : execOp.getChildOps()) {
1249-
getBackwardSlice(&childOp, &backwardSlice, bsOptions);
1250+
(void)getBackwardSlice(&childOp, &backwardSlice, bsOptions);
12501251
backwardSlice.insert(&childOp);
12511252
}
12521253
}

‎mlir/lib/Transform/AIRLowerLinalgTensors.cpp‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,10 @@ using namespace xilinx::air;
3333

3434
// Remove tensor_load followed by buffer_cast
3535
struct RemoveBufferCastPattern
36-
: public OpRewritePattern<bufferization::ToMemrefOp> {
37-
using OpRewritePattern<bufferization::ToMemrefOp>::OpRewritePattern;
36+
: public OpRewritePattern<bufferization::ToBufferOp> {
37+
using OpRewritePattern<bufferization::ToBufferOp>::OpRewritePattern;
3838

39-
LogicalResult matchAndRewrite(bufferization::ToMemrefOp op,
39+
LogicalResult matchAndRewrite(bufferization::ToBufferOp op,
4040
PatternRewriter &rewriter) const override {
4141

4242
auto load = op.getOperand().getDefiningOp<bufferization::ToTensorOp>();
@@ -151,7 +151,8 @@ void AIRLowerLinalgTensors::runOnOperation() {
151151
bufferization::BufferizationOptions options;
152152
options.opFilter.allowDialect<linalg::LinalgDialect>();
153153

154-
if (failed(bufferizeOp(getOperation(), options)))
154+
bufferization::BufferizationState state;
155+
if (failed(bufferizeOp(getOperation(), options, state)))
155156
signalPassFailure();
156157

157158
RewritePatternSet patterns1(&context);

‎mlir/lib/Util/Util.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1887,7 +1887,7 @@ void air::getBackwardSliceInRegion(OpBuilder builder, Region *region,
18871887
continue;
18881888
// Get backward slices
18891889
SetVector<Operation *> valBS;
1890-
getBackwardSlice(valDefOp, &valBS, bsOptions);
1890+
(void)getBackwardSlice(valDefOp, &valBS, bsOptions);
18911891
for (auto b : valBS) {
18921892
backwardSlices.insert(b);
18931893
}

‎mlir/test/Conversion/AIRRtToNpu/airrt_to_npu.mlir‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -360,8 +360,6 @@ module {
360360
// The key difference is that memref.alloc is removed.
361361

362362
// CHECK-LABEL: func13
363-
// CHECK-NOT: memref.alloc
364-
// CHECK: memref.assume_alignment
365363
// CHECK-SAME: memref<32xbf16>
366364
// CHECK-NOT: memref.alloc
367365
// CHECK: return

‎mlir/test/Transform/AIRAutomaticTiling/air_automatic_tiling_pass.mlir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
module {
1818
func.func @task(%arg0: tensor<28x10xf32>, %arg1: tensor<28x10xf32>) -> tensor<28x10xf32> {
1919
%0 = memref.alloc() : memref<28x10xf32>
20-
%1 = bufferization.to_memref %arg0 : tensor<28x10xf32> to memref<28x10xf32>
20+
%1 = bufferization.to_buffer %arg0 : tensor<28x10xf32> to memref<28x10xf32>
2121
affine.for %arg2 = 0 to 28 {
2222
affine.for %arg3 = 0 to 10 {
2323
%7 = affine.load %1[%arg2, %arg3] : memref<28x10xf32>
@@ -28,8 +28,8 @@ module {
2828
} {affine_opt_label = "affine_opt"}
2929
%2 = bufferization.to_tensor %0 : memref<28x10xf32> to tensor<28x10xf32>
3030
%3 = memref.alloc() : memref<28x10xf32>
31-
%4 = bufferization.to_memref %2 : tensor<28x10xf32> to memref<28x10xf32>
32-
%5 = bufferization.to_memref %arg1 : tensor<28x10xf32> to memref<28x10xf32>
31+
%4 = bufferization.to_buffer %2 : tensor<28x10xf32> to memref<28x10xf32>
32+
%5 = bufferization.to_buffer %arg1 : tensor<28x10xf32> to memref<28x10xf32>
3333
affine.for %arg2 = 0 to 28 {
3434
affine.for %arg3 = 0 to 10 {
3535
%7 = affine.load %4[%arg2, %arg3] : memref<28x10xf32>

‎mlir/test/Transform/AIRLinalgCodegen/air_linalg_codegen_matmul.mlir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@
1212
// CHECK-LABEL: func.func @task(
1313
// CHECK-SAME: %[[VAL_0:.*]]: tensor<128x128xi32>,
1414
// CHECK-SAME: %[[VAL_1:.*]]: tensor<128x128xi32>) -> tensor<128x128xi32> {
15-
// CHECK: %[[VAL_2:.*]] = bufferization.to_memref %[[VAL_0]]
16-
// CHECK: %[[VAL_3:.*]] = bufferization.to_memref %[[VAL_1]]
15+
// CHECK: %[[VAL_2:.*]] = bufferization.to_buffer %[[VAL_0]]
16+
// CHECK: %[[VAL_3:.*]] = bufferization.to_buffer %[[VAL_1]]
1717
// CHECK: %[[VAL_4:.*]] = memref.alloc() : memref<128x128xi32>
1818
// CHECK: %[[VAL_7:.*]] = arith.constant 0 : index
1919
// CHECK: %[[VAL_6:.*]] = arith.constant 128 : index
@@ -37,8 +37,8 @@
3737
// CHECK: }
3838
module {
3939
func.func @task(%arg0: tensor<128x128xi32>, %arg1: tensor<128x128xi32>) -> tensor<128x128xi32> {
40-
%0 = bufferization.to_memref %arg0 : tensor<128x128xi32> to memref<128x128xi32>
41-
%1 = bufferization.to_memref %arg1 : tensor<128x128xi32> to memref<128x128xi32>
40+
%0 = bufferization.to_buffer %arg0 : tensor<128x128xi32> to memref<128x128xi32>
41+
%1 = bufferization.to_buffer %arg1 : tensor<128x128xi32> to memref<128x128xi32>
4242
%2 = memref.alloc() : memref<128x128xi32>
4343
linalg.matmul ins(%0, %1 : memref<128x128xi32>, memref<128x128xi32>) outs(%2 : memref<128x128xi32>)
4444
%3 = bufferization.to_tensor %2 : memref<128x128xi32> to tensor<128x128xi32>

‎mlir/test/Transform/AIRLoopMerging/air_loop_merging_pass.mlir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
module {
1818
func.func @task(%arg0: tensor<28x10xf32>, %arg1: tensor<28x10xf32>) -> tensor<28x10xf32> {
1919
%0 = memref.alloc() : memref<28x10xf32>
20-
%1 = bufferization.to_memref %arg0 : tensor<28x10xf32> to memref<28x10xf32>
20+
%1 = bufferization.to_buffer %arg0 : tensor<28x10xf32> to memref<28x10xf32>
2121
affine.for %arg2 = 0 to 2 {
2222
affine.for %arg3 = 0 to 2 {
2323
affine.for %arg4 = 0 to 7 {
@@ -36,8 +36,8 @@ module {
3636
} {affine_opt_label = "affine_opt"}
3737
%2 = bufferization.to_tensor %0 : memref<28x10xf32> to tensor<28x10xf32>
3838
%3 = memref.alloc() : memref<28x10xf32>
39-
%4 = bufferization.to_memref %2 : tensor<28x10xf32> to memref<28x10xf32>
40-
%5 = bufferization.to_memref %arg1 : tensor<28x10xf32> to memref<28x10xf32>
39+
%4 = bufferization.to_buffer %2 : tensor<28x10xf32> to memref<28x10xf32>
40+
%5 = bufferization.to_buffer %arg1 : tensor<28x10xf32> to memref<28x10xf32>
4141
affine.for %arg2 = 0 to 5 {
4242
affine.for %arg3 = 0 to 2 {
4343
affine.for %arg4 = 0 to 7 {

‎mlir/test/Transform/AIRLoopPermutation/air_loop_permutation_pass.mlir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
module {
2020
func.func @task(%arg0: tensor<28x10xf32>, %arg1: tensor<28x10xf32>) -> tensor<28x10xf32> {
2121
%0 = memref.alloc() : memref<28x10xf32>
22-
%1 = bufferization.to_memref %arg0 : tensor<28x10xf32> to memref<28x10xf32>
22+
%1 = bufferization.to_buffer %arg0 : tensor<28x10xf32> to memref<28x10xf32>
2323
affine.for %arg2 = 0 to 2 {
2424
affine.for %arg3 = 0 to 2 {
2525
affine.for %arg4 = 0 to 7 {
@@ -38,8 +38,8 @@ module {
3838
} {affine_opt_label = "affine_opt"}
3939
%2 = bufferization.to_tensor %0 : memref<28x10xf32> to tensor<28x10xf32>
4040
%3 = memref.alloc() : memref<28x10xf32>
41-
%4 = bufferization.to_memref %2 : tensor<28x10xf32> to memref<28x10xf32>
42-
%5 = bufferization.to_memref %arg1 : tensor<28x10xf32> to memref<28x10xf32>
41+
%4 = bufferization.to_buffer %2 : tensor<28x10xf32> to memref<28x10xf32>
42+
%5 = bufferization.to_buffer %arg1 : tensor<28x10xf32> to memref<28x10xf32>
4343
affine.for %arg2 = 0 to 2 {
4444
affine.for %arg3 = 0 to 2 {
4545
affine.for %arg4 = 0 to 7 {

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