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AArch64 special register designations Change range of o0 to [0, 3] #342

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merged 2 commits into from
Oct 28, 2024

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@v01dXYZ v01dXYZ commented Aug 22, 2024

The documented syntax doesn't allow designation of all possible special registers (e.g. "ICC_CTLR_EL3" designated with "3:6:12:12:4").

clang supports the documented syntax but not gcc.

Both compilers support an alternative syntax with in [0, 3]: s<o0>_<o1>_c<CRm>_c<CRn>_<o2>.


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Redacted

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Thanks for the patch.

Can you please add an item in the section "Changes for next release"?

@vhscampos vhscampos added the bugfix Bug fixes label Sep 12, 2024
The documented syntax doesn't allow designation of all possible special registers (e.g. "ICC_CTLR_EL3" designated with "3:6:12:12:4").

clang supports the documented syntax but not gcc.

Both compilers support an alternative syntax with <o0> in [0, 3]: `s<o0>_<o1>_c<CRm>_c<CRn>_<o2>`.
@vhscampos vhscampos merged commit 1b6ea53 into ARM-software:main Oct 28, 2024
3 of 4 checks passed
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@all-contributors please add @v01dXYZ for content

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@vhscampos

I've put up a pull request to add @v01dXYZ! 🎉

vhscampos pushed a commit that referenced this pull request Oct 28, 2024
Adds @v01dXYZ as a contributor for content.

This was requested by vhscampos [in this
comment](#342 (comment))

[skip ci]

---------

Co-authored-by: allcontributors[bot] <46447321+allcontributors[bot]@users.noreply.github.com>
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