fix simulation models for dual-ported SRAMs with >=32 words#194
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Markussha wants to merge 1 commit intoAUCOHL:mainfrom
Open
fix simulation models for dual-ported SRAMs with >=32 words#194Markussha wants to merge 1 commit intoAUCOHL:mainfrom
Markussha wants to merge 1 commit intoAUCOHL:mainfrom
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Hi,
I've noticed during simulation, that I was unable to use the read port of RAM32_1RW1R. After some digging, I've found that the port has been left dangling. This PR adds a RAM16_1RW1R model and fixes RAM32_1RW1R. I've tested both models in Questa and they seem to work.
As I am not entirely aware what the additional files in the model directory do (e.g. config.yml), I hope that this change is beneficial to you :)