This repository contains notes from the NPTEL course "RTL-to-GDS Design Flow".
- 📘 Instructor: Prof. Sneh Saurabh
- 🏫 Institute: IIIT Delhi
- 🎓 Platform: NPTEL
The course explains the full backend VLSI design process — from RTL (Register Transfer Level) to GDSII file generation. Topics include logic synthesis, placement, routing, timing analysis, and more.
Notes will be updated weekly. Feel free to use and refer to these notes