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@bsdjhb bsdjhb commented Oct 16, 2024

The drivers have been disconnected from the build since the removal of
the SOCFPGA kernel configs.

The drivers have been disconnected from the build since the removal of
the SOCFPGA kernel configs.
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bsdjhb commented Oct 16, 2024

I plan to do this upstream, this PR is mostly just to ensure our CI doesn't trip over anything. I do need to ensure this doesn't remove anything we depend on for our FPGA setups.

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bsdjhb commented Oct 23, 2024

@jonwoodruff, @bukinr I believe from the recent discussion on Slack, our modern FPGA images use VirtIO for I/O instead of Altera IP blocks, so that we don't use any of these drivers currently (including atse(4)) and that we don't plan on using them in the future?

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rwatson commented Mar 20, 2025

At least for Xilinx, getting FPGAs without hard processor cores remains quite possible (and common?). I'm not sure if this is true for Intel (now Altera) FPGAs or not.

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bsdjhb commented Mar 24, 2025

I've already removed these upstream.

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