Skip to content
View Carl7yan's full-sized avatar
🎯
Focusing
🎯
Focusing
  • Xidian University
  • 06:22 (UTC +08:00)

Block or report Carl7yan

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Carl7yan/README.md

Hi there 👋

About Me

  • Hi, I'm Shengjie, a digital IC verification engineer with 1 year of internship experience.
  • I‘m passionate about using GitHub to collaborate with others and giving back to the community.

Contact Me

Popular repositories Loading

  1. hello-world hello-world Public archive

    Hi, I'm Carl. Nice to meet you guys! @_@

    1

  2. apb-uart-uvm-env apb-uart-uvm-env Public

    Forked from Lampro-Mellon/apb-uart-uvm-env

    SystemVerilog 1

  3. Carl7yan Carl7yan Public

  4. Viterbi-Decoder-in-Verilog Viterbi-Decoder-in-Verilog Public

    Forked from jfoshea/Viterbi-Decoder-in-Verilog

    An efficient implementation of the Viterbi decoding algorithm in Verilog

    Verilog