[Feat] Hardware Generation For Differentiable Logic Networks (ADLS Group 1)

[samuelpswang]

Description

Recently proposed Deep Differentiable Logic Gate Networks (DiffLogic) provide state of the art performance while keeping the network size small and the hardware requirements low. This pull request implements the key components of the logic gate network in hardware for Mase.

Key Contributions

• Implemented PyTorch-custom-module-mapped parameterised hardware and their test-benches, namely fixed_difflogic_logic.sv (mapping to LogicLayer module) and fixed_difflogic_groupsum.sv (mapping to GroupSum module).
• Connected hardware to Mase hardware emit passes for automatic hardware generation and test-bench generation, including modifications to emit_verilog_top_transform_pass and emit_cocotb_transform_pass.

Usage

• Detailed information, including an introduction on DiffLogic, a tutorial on generating hardware for a MNIST DiffLogic model, and modification information for each function, can be found in src/tutorials/difflogic/demo.ipynb.

References

• difflogic - A Library for Differentiable Logic Gate Networks (Petersen, et al., 2024): github.com/Felix-Petersen/difflogic
• Deep Differentiable Logic Gate Networks (Petersen, et al., 2022): arxiv.org/pdf/2210.08277

[jianyicheng]

Thanks for contributing to MASE! This is excellent work!

I think your PR is technically strong, and only require minor changes to be merged into the main branch. Please see my detailed comments.

[jianyicheng]

I think this is specific to your machine, right? You can make this general in two ways:

1. write a script to clone from an open-source repo (with a specific commit) at the installation
2. include them as submodules

[samuelpswang]

Removed for now (8360889), those were configurations of mappings from local directories into the Docker container left in by accident. The used repo (difflogic) was not a direct dependancy of the features we developed, so I don't think we have to make it as a submodule, right?