🧠 Instruction Parallelism & Superscalar CPU Simulation

This project explores how modern superscalar CPUs execute instructions in parallel while handling data and control hazards. We analyze a Python function and simulate how instructions are scheduled, issued, executed, and committed using advanced CPU features.

🔍 Key Concepts

• Instruction-Level Parallelism (ILP)
• Data Hazards (RAW, WAR, WAW)
• Control Hazards (branch prediction)
• Superscalar Execution (multi-issue)
• Out-of-Order Execution
• Register Renaming
• Reorder Buffer (ROB) Simulation

🧩 Code Under Analysis

def do_something(a, b):
  x = a + b
  y = a * b
  z = x / y
  if x > y:
    x = x + 3
  y = y + 2

Credit: Codecademy

📊 Visualizations

• Gantt-style pipeline diagrams showing instruction parallelism
• ROB (Reorder Buffer) state tables with issue, execution, and commit cycles

📁 Included Files

• superscalar_gantt.png – Execution timeline diagram
• rob_simulation.py – Python script modeling the ROB
• rob_latex_table.tex – LaTeX-formatted ROB table for academic reports

🚀 Highlights

• Models realistic instruction dispatching and commit via ROB
• Demonstrates how CPUs speculatively execute and recover from branch mispredictions
• Explains how hazards are detected and resolved in real-world pipelines

📌 Usage

Use this analysis for:

• Learning how out-of-order CPUs schedule and resolve instruction hazards
• Teaching parallel architecture concepts
• Writing performance-aware low-level software

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“Instruction-level parallelism is not just about speed — it’s about making every cycle count.”

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