DSSS Wireless Transmit-Receive System

This repository contains the VHDL files for the course "Digital Synthese: practica" by Jan Meel (KU Leuven, Campus De Nayer).

Files

Total (top file)
Transmitter (top file)
- access layer: PNGenerator, MUX
- datalink layer: SequenceController, DataRegister
- application layer: EdgeDetector, UpDownCounter, Debouncer, SegDecoder
Receiver (top file)
- access layer: SegDecoder, DataLatch
- datalink layer: DataShiftReg
- application layer: DPLL, MatchedFilter, Correlator, Despreader, MUX, PNGenerator, Edgedetector
Hardware
- transmitter: Xilinx UCF file, Transmitter hardware top file
- receiver: Xilinx UCF file, Receiver hardware top file

A fully working DSSS Wireless Transmit-Receive System with 3 different PN codes.

Everything in this repository is available under the GPLv3 License.

Name		Name	Last commit message	Last commit date
Latest commit History 65 Commits
docs		docs
hardware		hardware
receiver		receiver
transmitter		transmitter
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
total.vhd		total.vhd
total_test.vhd		total_test.vhd