Add control inputs to reg stage

.gitignore

@@ -1,3 +1,7 @@
 generated
 build
 fusesoc_libraries
+
+# Generated by scala
+.bsp
+targer

chisel/src/main/scala/riscv/stage/Alu.scala

@@ -24,6 +24,36 @@ class AluIo(width: Int) extends Bundle {
   val out = Output(UInt(width.W))
 }
 
+class AluStageControl extends Bundle {
+  val sel = Input(AluSel())
+}
+
+class AluStageIn(width: Int) extends Bundle {
+  val a = Input(UInt(width.W))
+  val b = Input(UInt(width.W))
+  val aluControl = Input(new AluStageControl)
+}
+
+class AluStageOut(width: Int) extends Bundle {
+  val out = Output(UInt(width.W))
+}
+
+class AluStageIO(width: Int) extends Bundle {
+  val in = Input(new AluStageIn(width))
+  val out = Output(new AluStageOut(width))
+}
+
+class AluStage(width: Int) extends Module {
+  val io = IO(new AluStageIO(width))
+
+  val alu = new Alu(width)
+  alu.io.a := io.in.a
+  alu.io.b := io.in.b
+  alu.io.sel := io.in.aluControl.sel
+
+  io.out.out := alu.io.out
+}
+
 class Alu(width: Int) extends Module {
   val io = IO(new AluIo(width))
 

chisel/src/main/scala/riscv/stage/DataMem.scala

@@ -18,6 +18,39 @@ class DataMemIo(width: Int) extends Bundle {
   val renOut = Output(Bool()) /* Read enable */
 }
 
+class DataMemStageControl extends Bundle {
+  val wen = Input(Bool()) /* Write enable */
+  val ren = Input(Bool()) /* Read enable */
+}
+
+class DataMemStageIn(width: Int) extends Bundle {
+  val din = Input(UInt(width.W))
+  val addr = Input(UInt(width.W))
+  val control = Input(new DataMemStageControl)
+}
+
+class DataMemStageOut(width: Int) extends Bundle {
+  val dinOut = Output(UInt(width.W))
+  val addrOut = Output(UInt(width.W))
+  val wenOut = Output(Bool()) /* Write enable */
+  val renOut = Output(Bool()) /* Read enable */
+}
+
+class DataMemStageIO(width: Int) extends Bundle {
+  val in = Input(new DataMemStageIn(width))
+  val out = Output(new DataMemStageOut(width))
+}
+
+//class DataMemStage(width: Int) extends Bundle {
+//  val io = IO(new DataMemStageIO(width))
+//  val mem = Module(new DataMem())
+//
+//  io.out.dinOut := mem.io.dinOut
+//  io.out.addrOut := mem.io.addrOut
+//  io.out. := mem.io.
+//  io.out. := mem.io.
+//}
+
 class DataMem(width: Int) extends Module {
   val io = IO(new DataMemIo(width))
 

chisel/src/main/scala/riscv/stage/reg/Reg.scala

@@ -0,0 +1,50 @@
+package riscv.stage.reg
+
+import riscv.stage.regfile.Regfile
+import chisel3._
+import chisel3.util._
+
+/* Control inputs */
+class RegStageControl(numregs: Int, width: Int) extends Bundle {
+  val selectWidth = log2Ceil(numregs).W
+  val s1 = Input(UInt(selectWidth))
+  val s2 = Input(UInt(selectWidth))
+  val sd = Input(UInt(selectWidth))
+}
+
+class WbStageControl extends Bundle {
+  val wen = Input(Bool())
+}
+
+/* IO */
+class RegStageIn(numregs: Int, width: Int) extends Bundle {
+  val controlReg = Input(new RegStageControl(numregs, width))
+  val controlWb = Input(new WbStageControl)
+  val din = Input(UInt(width.W));
+}
+
+class RegStageOut(width: Int) extends Bundle {
+  val rs1 = Output(UInt(width.W))
+  val rs2 = Output(UInt(width.W))
+}
+
+class RegStageIO(numregs: Int, width: Int) extends Bundle {
+  val in = Input(new RegStageIn(numregs, width))
+  val out = Output(new RegStageOut(width))
+}
+
+class RegStage(numregs: Int, width: Int) extends Module { 
+  val io = IO(new RegStageIO(numregs, width))
+
+  val regfile = Module(new Regfile(numregs, width))
+
+  regfile.io.s1 := io.in.controlReg.s1
+  regfile.io.s2 := io.in.controlReg.s2
+  regfile.io.sd := io.in.controlReg.sd
+  regfile.io.din := io.in.din
+  regfile.io.wen := io.in.controlWb.wen
+
+  io.out.rs1 := regfile.io.rs1
+  io.out.rs2 := regfile.io.rs2
+}
+

chisel/src/main/scala/riscv/stage/Regfile.scala → chisel/src/main/scala/riscv/stage/reg/Regfile.scala

@@ -15,7 +15,6 @@ class RegIo(numregs: Int, width: Int) extends Bundle {
   val rs2 = Output(UInt(width.W))
 }
 
-
 class Regfile(numregs: Int, width: Int) extends Module {
   val io = IO(new RegIo(numregs, width))
 

chisel/src/main/scala/toplevel/TopLevel.scala

@@ -4,7 +4,6 @@ import chisel3._
 import blinky.Blinky
 import circt.stage.ChiselStage
 import pll.Pll
-import riscv.stage.regfile
 
 class TopLevel extends Module {
   val led0 = IO(Output(Bool()))

chisel/src/test/scala/riscv/stage/RegfileSpec.scala → chisel/src/test/scala/riscv/stage/reg/RegfileSpec.scala

@@ -1,4 +1,4 @@
-package riscv.stage.regfile
+package riscv.stage.reg.regfile
 
 import chisel3._
 import chiseltest._