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2020.1 Vitis™ - Hardware Accelerators Tutorials

See Vitis™ Development Environment on xilinx.com

Introduction to Vitis Hardware Accelerators

Tutorial Description
Introduction to Vitis Hardware Accelerators This tutorial puts in practice the concepts of FPGA acceleration and illustrates how to gradually optimize a hardware accelerator implementing the Cholesky matrix decomposition algorithm.

Design Tutorials

The methodology for developing optimized accelerated applications is comprised of two major phases: architecting the application, and developing the hardware kernels. In the first phase, you make key decisions about the application architecture by determining which software functions should be accelerated onto FPGA kernels, how much parallelism can be achieved, and how to deliver it in code. In the second phase, you implement the kernels by structuring the source code, and applying the necessary compiler options and pragmas to create the kernel architecture needed to achieve the optimized performance target. The following examples illustrate the use of this methodology in real-world applications.

Tutorial Description
Bloom Filter Example This tutorial shows how to achieve a 10x speed-up on a data analytics application using a combination of kernel and host code optimization techniques.
Convolution Example This tutorial walks through the process of analyzing and optimizing a 2D convolution used for real-time processing of a video stream.
RTL Systems Integration Example This tutorial demonstrates how to integrate free-running RTL kernels, Vitis Library functions, and custom Vitis HLS kernels into a real system.

Feature Tutorials

Tutorial Description
Getting Started with RTL Kernels This tutorial demonstrates how to use the Vitis core development kit to program an RTL kernel into an FPGA and build a Hardware Emulation using a common development flow.
Mixing C and RTL This tutorial demonstrates how to work with an application containing RTL and C kernels, along with various design analysis features.

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