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Fix bug when mixed mode SMC yields zero forward or zero reverse passes #83

Fix bug when mixed mode SMC yields zero forward or zero reverse passes

Fix bug when mixed mode SMC yields zero forward or zero reverse passes #83

Triggered via pull request October 1, 2025 20:11
Status Failure
Total duration 1m 52s
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PreCommit.yml

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1 error and 1 warning
pre-commit
Process completed with exit code 1.
pre-commit
No file matched to [/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/*requirements*.txt,/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/*requirements*.in,/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/*constraints*.txt,/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/*constraints*.in,/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/pyproject.toml,/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/uv.lock,/home/runner/work/DifferentiationInterface.jl/DifferentiationInterface.jl/**/*.py.lock]. The cache will never get invalidated. Make sure you have checked out the target repository and configured the cache-dependency-glob input correctly.