Atualizando para "processor_ci"

LSC-Unicamp · Feb 5, 2025 · e399a7b · e399a7b
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diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
@@ -11,8 +11,8 @@ Thank you for considering contributing to the project! We’re happy to welcome
    Clone your forked repository to your local development environment.  
 
    ```bash  
-   git clone https://github.com/YOUR_USERNAME/processor-ci.git  
-   cd processor-ci  
+   git clone https://github.com/YOUR_USERNAME/processor_ci.git  
+   cd processor_ci  
    ```  
 
 3. **Create a Branch**  
@@ -83,4 +83,4 @@ Thank you for considering contributing to the project! We’re happy to welcome
 
 ## License  
 
-By contributing to this project, you agree that your contributions will be licensed under the same license as the project. See the [license](https://github.com/LSC-Unicamp/processor-ci/blob/main/LICENSE) for details.  
+By contributing to this project, you agree that your contributions will be licensed under the same license as the project. See the [license](https://github.com/LSC-Unicamp/processor_ci/blob/main/LICENSE) for details.  
diff --git a/README.md b/README.md
@@ -1,7 +1,7 @@
 # ProcessorCI
 
-[![Pylint](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/pylint.yml/badge.svg)](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/pylint.yml)  
-[![Python Code Format Check](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/blue.yml/badge.svg)](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/blue.yml)  
+[![Pylint](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/pylint.yml/badge.svg)](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/pylint.yml)  
+[![Python Code Format Check](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/blue.yml/badge.svg)](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/blue.yml)  
 
 - **Não fala Inglês? [clique aqui](./README.pt.md)**
 
@@ -21,8 +21,8 @@ This repository contains utility scripts to configure processors, perform synthe
 Clone the repository to your local development environment:
 
 ```bash
-git clone https://github.com/LSC-Unicamp/processor-ci.git  
-cd processor-ci
+git clone https://github.com/LSC-Unicamp/processor_ci.git  
+cd processor_ci
 ```
 
 2. **Set up a Virtual Environment and Install Dependencies**  
@@ -127,7 +127,7 @@ Core #(
 );
 ```
 
-More details are available in the [Controller documentation](https://lsc-unicamp.github.io/processor-ci-controller/).  
+More details are available in the [Controller documentation](https://lsc-unicamp.github.io/processor_ci-controller/).  
 
 #### 3. Integrating with Jenkins  
 

diff --git a/README.pt.md b/README.pt.md
@@ -1,7 +1,7 @@
 # ProcessorCI
 
-[![Pylint](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/pylint.yml/badge.svg)](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/pylint.yml)  
-[![Python Code Format Check](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/blue.yml/badge.svg)](https://github.com/LSC-Unicamp/processor-ci/actions/workflows/blue.yml)  
+[![Pylint](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/pylint.yml/badge.svg)](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/pylint.yml)  
+[![Python Code Format Check](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/blue.yml/badge.svg)](https://github.com/LSC-Unicamp/processor_ci/actions/workflows/blue.yml)  
 
 Bem-vindo ao ProcessorCI!
 
@@ -19,8 +19,8 @@ Este repositório contém scripts utilitários para configurar processadores, re
 Clone o repositório para o seu ambiente de desenvolvimento local.
 
 ```bash
-git clone https://github.com/LSC-Unicamp/processor-ci.git  
-cd processor-ci  
+git clone https://github.com/LSC-Unicamp/processor_ci.git  
+cd processor_ci  
 ```
 
 2. **Configure um ambiente virtual e instale as dependências**  
@@ -125,7 +125,7 @@ Core #(
 );
 ```
 
-Mais detalhes na [documentação do Controller](https://lsc-unicamp.github.io/processor-ci-controller/).  
+Mais detalhes na [documentação do Controller](https://lsc-unicamp.github.io/processor_ci-controller/).  
 
 #### 3. Integrando ao Jenkins  
 

diff --git a/config_generator.py b/config_generator.py
@@ -95,7 +95,7 @@
     # "digilent_arty_a7_100t"
 ]
 DESTINATION_DIR = './temp'
-MAIN_SCRIPT_PATH = '/eda/processor-ci/main.py'
+MAIN_SCRIPT_PATH = '/eda/processor_ci/main.py'
 
 
 def get_top_module_file(modules: list[dict[str, str]], top_module: str) -> str:

diff --git a/core/fpga.py b/core/fpga.py
@@ -126,7 +126,7 @@ def make_build_file(config: dict, board: str, toolchain_path: str) -> str:
         toolchain_path = toolchain_path[:-1]
 
     base_config_path = (
-        f'{toolchain_path}/processor-ci/build_scripts/{board}.tcl'
+        f'{toolchain_path}/processor_ci/build_scripts/{board}.tcl'
     )
 
     if not os.path.exists(base_config_path):
@@ -150,7 +150,7 @@ def make_build_file(config: dict, board: str, toolchain_path: str) -> str:
         prefix = get_prefix(board, False, False)
         file.write(
             prefix
-            + f' {toolchain_path}/processor-ci/rtl/{config["folder"]}.v\n'
+            + f' {toolchain_path}/processor_ci/rtl/{config["folder"]}.v\n'
         )
 
         for i in config['files']:
@@ -184,7 +184,7 @@ def build(build_script_path: str, board: str, toolchain_path: str) -> None:
     if toolchain_path[-1] == '/':
         toolchain_path = toolchain_path[:-1]
 
-    makefile_path = f'{toolchain_path}/processor-ci/makefiles/{board}.mk'
+    makefile_path = f'{toolchain_path}/processor_ci/makefiles/{board}.mk'
 
     macros = get_macros(board)
 
@@ -232,7 +232,7 @@ def flash(board: str, toolchain_path: str) -> None:
     if toolchain_path[-1] == '/':
         toolchain_path = toolchain_path[:-1]
 
-    makefile_path = f'{toolchain_path}/processor-ci/makefiles/{board}.mk'
+    makefile_path = f'{toolchain_path}/processor_ci/makefiles/{board}.mk'
 
     with subprocess.Popen(
         ['make', '-f', makefile_path, 'load'],

diff --git a/core/jenkins.py b/core/jenkins.py
@@ -106,8 +106,8 @@ def generate_jenkinsfile(
 
     # Command for extra utilities in the pipeline
     utilities_command = (
-        r'sh "python3 /eda/processor-ci/core/labeler_prototype.py -d \$(pwd) '
-        + '-c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json"'
+        r'sh "python3 /eda/processor_ci/core/labeler_prototype.py -d \$(pwd) '
+        + '-c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json"'
     )
 
     # Determine simulation command based on file types

diff --git a/jenkins_pipeline/.Jenkinsfile b/jenkins_pipeline/.Jenkinsfile
@@ -22,7 +22,7 @@ pipeline {
          stage('Utilities')  {
             steps {
                 dir("") {
-                    sh "python3 /eda/processor-ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json"
+                    sh "python3 /eda/processor_ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json"
                 }            
             }
         }
@@ -39,7 +39,7 @@ pipeline {
                             steps {
                                 dir("") {
                                     echo 'Starting synthesis for FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p  -b colorlight_i9'
                                 }
                             }
@@ -48,7 +48,7 @@ pipeline {
                             steps {
                                 dir("") {
                                     echo 'Flashing FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p  -b colorlight_i9 -l'
                                 }
                             }
@@ -73,7 +73,7 @@ pipeline {
                             steps {
                                 dir("") {
                                     echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p  -b digilent_nexys4_ddr'
                                 }
                             }
@@ -82,7 +82,7 @@ pipeline {
                             steps {
                                 dir("") {
                                     echo 'Flashing FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p  -b digilent_nexys4_ddr -l'
                                 }
                             }

diff --git a/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile b/jenkins_pipeline/AUK-V-Aethia.Jenkinsfile
@@ -22,7 +22,7 @@ pipeline {
          stage('Utilities')  {
             steps {
                 dir("AUK-V-Aethia") {
-                    sh "python3 /eda/processor-ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json"
+                    sh "python3 /eda/processor_ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json"
                 }            
             }
         }
@@ -39,7 +39,7 @@ pipeline {
                             steps {
                                 dir("AUK-V-Aethia") {
                                     echo 'Starting synthesis for FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p AUK-V-Aethia -b colorlight_i9'
                                 }
                             }
@@ -48,7 +48,7 @@ pipeline {
                             steps {
                                 dir("AUK-V-Aethia") {
                                     echo 'Flashing FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p AUK-V-Aethia -b colorlight_i9 -l'
                                 }
                             }
@@ -73,7 +73,7 @@ pipeline {
                             steps {
                                 dir("AUK-V-Aethia") {
                                     echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p AUK-V-Aethia -b digilent_nexys4_ddr'
                                 }
                             }
@@ -82,7 +82,7 @@ pipeline {
                             steps {
                                 dir("AUK-V-Aethia") {
                                     echo 'Flashing FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p AUK-V-Aethia -b digilent_nexys4_ddr -l'
                                 }
                             }

diff --git a/jenkins_pipeline/Anfield.Jenkinsfile b/jenkins_pipeline/Anfield.Jenkinsfile
@@ -22,7 +22,7 @@ pipeline {
          stage('Utilities')  {
             steps {
                 dir("Anfield") {
-                    sh "python3 /eda/processor-ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json"
+                    sh "python3 /eda/processor_ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json"
                 }            
             }
         }
@@ -39,7 +39,7 @@ pipeline {
                             steps {
                                 dir("Anfield") {
                                     echo 'Starting synthesis for FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Anfield -b colorlight_i9'
                                 }
                             }
@@ -48,7 +48,7 @@ pipeline {
                             steps {
                                 dir("Anfield") {
                                     echo 'Flashing FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Anfield -b colorlight_i9 -l'
                                 }
                             }
@@ -73,7 +73,7 @@ pipeline {
                             steps {
                                 dir("Anfield") {
                                     echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Anfield -b digilent_nexys4_ddr'
                                 }
                             }
@@ -82,7 +82,7 @@ pipeline {
                             steps {
                                 dir("Anfield") {
                                     echo 'Flashing FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Anfield -b digilent_nexys4_ddr -l'
                                 }
                             }

diff --git a/jenkins_pipeline/Baby-Risco-5.Jenkinsfile b/jenkins_pipeline/Baby-Risco-5.Jenkinsfile
@@ -22,7 +22,7 @@ pipeline {
          stage('Utilities')  {
             steps {
                 dir("Baby-Risco-5") {
-                    sh "python3 /eda/processor-ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json"
+                    sh "python3 /eda/processor_ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json"
                 }            
             }
         }
@@ -39,7 +39,7 @@ pipeline {
                             steps {
                                 dir("Baby-Risco-5") {
                                     echo 'Starting synthesis for FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Baby-Risco-5 -b colorlight_i9'
                                 }
                             }
@@ -48,7 +48,7 @@ pipeline {
                             steps {
                                 dir("Baby-Risco-5") {
                                     echo 'Flashing FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Baby-Risco-5 -b colorlight_i9 -l'
                                 }
                             }
@@ -73,7 +73,7 @@ pipeline {
                             steps {
                                 dir("Baby-Risco-5") {
                                     echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Baby-Risco-5 -b digilent_nexys4_ddr'
                                 }
                             }
@@ -82,7 +82,7 @@ pipeline {
                             steps {
                                 dir("Baby-Risco-5") {
                                     echo 'Flashing FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Baby-Risco-5 -b digilent_nexys4_ddr -l'
                                 }
                             }

diff --git a/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile b/jenkins_pipeline/Cores-SweRV-EH2.Jenkinsfile
@@ -22,7 +22,7 @@ pipeline {
          stage('Utilities')  {
             steps {
                 dir("Cores-SweRV-EH2") {
-                    sh "python3 /eda/processor-ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json"
+                    sh "python3 /eda/processor_ci/core/labeler_prototype.py -d \$(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json"
                 }            
             }
         }
@@ -39,7 +39,7 @@ pipeline {
                             steps {
                                 dir("Cores-SweRV-EH2") {
                                     echo 'Starting synthesis for FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Cores-SweRV-EH2 -b colorlight_i9'
                                 }
                             }
@@ -48,7 +48,7 @@ pipeline {
                             steps {
                                 dir("Cores-SweRV-EH2") {
                                     echo 'Flashing FPGA colorlight_i9.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Cores-SweRV-EH2 -b colorlight_i9 -l'
                                 }
                             }
@@ -73,7 +73,7 @@ pipeline {
                             steps {
                                 dir("Cores-SweRV-EH2") {
                                     echo 'Starting synthesis for FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Cores-SweRV-EH2 -b digilent_nexys4_ddr'
                                 }
                             }
@@ -82,7 +82,7 @@ pipeline {
                             steps {
                                 dir("Cores-SweRV-EH2") {
                                     echo 'Flashing FPGA digilent_nexys4_ddr.'
-                                sh 'python3 /eda/processor-ci/main.py -c /eda/processor_ci/config.json \
+                                sh 'python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json \
                                             -p Cores-SweRV-EH2 -b digilent_nexys4_ddr -l'
                                 }
                             }