Digital design and UVM-based functional verification for single-port RAM in SystemVerilog using Mentor QuestaSim. The repository contains the SPRAM design, all the UVM components and objects, an interface, and a package in addition to a testbench top module. Additionally, a do file is provided for execution using QuestaSim.
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Digital design and UVM-based functional verification for single-port RAM in SystemVerilog using Mentor QuestaSim.
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MarwanEid1/UVM-SPRAM
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Digital design and UVM-based functional verification for single-port RAM in SystemVerilog using Mentor QuestaSim.
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