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Merge pull request #186 from kleinesfilmroellchen/antlr-and-test-fixes
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tests+verilog preproc: Fix ANTLR <=4.9, CMake and Icarus tests
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Nic30 authored Jan 14, 2024
2 parents 4bcce70 + ec7a130 commit a3f978c
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Showing 3 changed files with 6 additions and 1 deletion.
2 changes: 2 additions & 0 deletions src/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@
# build of the main library
##############################################################################################

set(CMAKE_CXX_STANDARD 17)

include(${CMAKE_CURRENT_SOURCE_DIR}/CMake_antlr4.txt)

include_directories(
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4 changes: 3 additions & 1 deletion src/verilogPreproc/verilogPreproc.cpp
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@@ -1,3 +1,5 @@
#include <any>

#include <hdlConvertor/verilogPreproc/verilogPreproc.h>

// antlr4-runtime/
Expand Down Expand Up @@ -194,7 +196,7 @@ antlrcpp::Any VerilogPreproc::visitDefine(
vector<MacroDefVerilog::param_info_t> params_dummy;
if (da) {
#if !defined(ANTLRCPP_VERSION_MAJOR) || (ANTLRCPP_VERSION_MAJOR == 4 && ANTLRCPP_VERSION_MINOR <= 9)
params = visitDefine_args(da);
params = visitDefine_args(da).as<vector<MacroDefVerilog::param_info_t> *>();
#else
params = std::any_cast<vector<MacroDefVerilog::param_info_t> *>(visitDefine_args(da));
#endif
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1 change: 1 addition & 0 deletions tests/test_icarus_verilog_testsuite.py
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Expand Up @@ -48,6 +48,7 @@ def parse_verilator_record(line, dir_name):
"sv_string_index": "string_index",
"sv_timeunit_prec": "sv_timeunit_prec1",
"sv_timeunit_prec_fail": "sv_timeunit_prec_fail1",
"sv_macro3": "sv_macro3a"
}
name = name_fix.get(name, name)
args = columns[1]
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