test: update basic_hdl_sim_model test files to new hwt names

Nic30 · Jun 6, 2024 · d623bc8 · d623bc8
1 parent 45bc7f8
commit d623bc8
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/tests/basic_hdl_sim_model/expected/simple_subunit.py.txt b/tests/basic_hdl_sim_model/expected/simple_subunit.py.txt
@@ -20,7 +20,7 @@ class submodule0(BasicRtlSimModel):
         # internal signals
         # component instances
     def _init_body(self):
-        self._interfaces = (
+        self._hwIOs = (
             self.io.a,
             self.io.b,
         )
@@ -61,7 +61,7 @@ class SimpleSubunit(BasicRtlSimModel):
     def _init_body(self):
         connectSimPort(self, self.submodule0_inst, "sig_submodule0_a", "a")
         connectSimPort(self, self.submodule0_inst, "sig_submodule0_b", "b")
-        self._interfaces = (
+        self._hwIOs = (
             self.io.a,
             self.io.b,
             self.io.sig_submodule0_a,