Cadnip.jl

Circuit Analysis & Differentiable Numerical Integration Program

Cadnip is an MNA-based analog circuit simulator written in Julia, focused on simplicity, maintainability, and robustness. It is a fork of CedarSim that replaces the DAECompiler backend with a straightforward Modified Nodal Analysis (MNA) implementation.

Features

• Import of multi-dialect SPICE/Spectre netlists
• Import of Verilog-A models
• DC and transient analyses
• Full differentiability via ForwardDiff (for sensitivities, optimization, ML, etc.)
• Parameter sweeps with CircuitSweep
• Works with standard Julia releases (1.11+)

Installation

Install from GitHub by first adding the subpackages, then the main package:

using Pkg
Pkg.add(url="https://github.com/NyanCAD/Cadnip.jl", subdir="Lexers.jl")
Pkg.add(url="https://github.com/NyanCAD/Cadnip.jl", subdir="SpectreNetlistParser.jl")
Pkg.add(url="https://github.com/NyanCAD/Cadnip.jl", subdir="VerilogAParser.jl")
Pkg.add(url="https://github.com/NyanCAD/Cadnip.jl")

Or clone and develop locally:

git clone https://github.com/NyanCAD/Cadnip.jl
cd Cadnip.jl
julia --project=. -e 'using Pkg; Pkg.instantiate()'

Quick Start

using CedarSim
using CedarSim.MNA: MNACircuit, MNASpec, voltage

# Define a circuit using SPICE syntax
# Note: SPICE requires a title line as the first line
builder = sp"""
* Voltage divider circuit
V1 vcc 0 DC 5
R1 vcc out 1k
R2 out 0 1k
"""

# Create circuit and run DC analysis
circuit = MNACircuit(builder)
sol = dc!(circuit)

# Access results
println("Output voltage: ", voltage(sol, :out))  # 2.5V (voltage divider)

Testing

Run the test suite:

julia --project=. -e 'using Pkg; Pkg.test()'

Or run specific test groups:

julia --project=. -e 'using Pkg; Pkg.test(test_args=["mna"])'

License

This package is available under the MIT license (see LICENSE.MIT). You may also use it under CERN-OHL-S v2 if that better suits your project.

Contributions are welcome! Please open an issue or pull request on GitHub.

Related Projects

• SpiceArmyKnife.jl - Tool for parsing and converting between netlist languages
• VerilogAParser.jl - Verilog-A parser
• SpectreNetlistParser.jl - Spectre netlist parser