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Tang-HaojinTang-Haojin
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build: bump to chisel 6 and fix deprecation warning (#360)
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13 files changed

+61
-101
lines changed

13 files changed

+61
-101
lines changed

‎HuanCun

‎Makefile

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,17 +23,16 @@ CHI_TOP_ARGS = --issue $(ISSUE) --core $(NUM_CORE) --tl-ul $(NUM_TL_UL) --bank $
2323
--chiseldb $(WITH_CHISELDB) --tllog $(WITH_TLLOG) --chilog $(WITH_CHILOG) \
2424
--fpga $(FPGA)
2525
BUILD_DIR = ./build
26-
TOP_V = $(BUILD_DIR)/$(TOP).v
27-
SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(TOP):-o:$(TOP).v.conf
26+
TOP_V = $(BUILD_DIR)/$(TOP).sv
2827
MEM_GEN = ./scripts/vlsi_mem_gen
2928
MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
3029

3130
gen-test-top:
32-
mill -i CoupledL2.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR) $(SIM_MEM_ARGS)
31+
mill -i CoupledL2.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR) --target systemverilog --split-verilog
3332
$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
3433

3534
gen-test-top-chi:
36-
mill -i CoupledL2.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR) $(SIM_MEM_ARGS) $(CHI_TOP_ARGS)
35+
mill -i CoupledL2.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR) $(CHI_TOP_ARGS) --target systemverilog --split-verilog
3736
$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
3837

3938
test-top-l2:

‎build.sc

Lines changed: 15 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -9,31 +9,24 @@ import $file.`rocket-chip`.common
99
import $file.`rocket-chip`.cde.common
1010
import $file.`rocket-chip`.hardfloat.build
1111

12-
val defaultVersions = Map(
13-
"chisel3" -> "3.6.0",
14-
"chisel3-plugin" -> "3.6.0",
15-
"chiseltest" -> "0.6.2",
16-
"scala" -> "2.13.10",
17-
)
12+
val defaultScalaVersion = "2.13.15"
1813

19-
def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = {
20-
val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
21-
if (cross)
22-
ivy"$org:::$dep:$version"
23-
else
24-
ivy"$org::$dep:$version"
25-
}
14+
def defaultVersions = Map(
15+
"chisel" -> ivy"org.chipsalliance::chisel:6.6.0",
16+
"chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.6.0",
17+
"chiseltest" -> ivy"edu.berkeley.cs::chiseltest:6.0.0"
18+
)
2619

2720
trait HasChisel extends ScalaModule {
2821
def chiselModule: Option[ScalaModule] = None
2922

3023
def chiselPluginJar: T[Option[PathRef]] = None
3124

32-
def chiselIvy: Option[Dep] = Some(getVersion("chisel3"))
25+
def chiselIvy: Option[Dep] = Some(defaultVersions("chisel"))
3326

34-
def chiselPluginIvy: Option[Dep] = Some(getVersion("chisel3-plugin", cross=true))
27+
def chiselPluginIvy: Option[Dep] = Some(defaultVersions("chisel-plugin"))
3528

36-
override def scalaVersion = defaultVersions("scala")
29+
override def scalaVersion = defaultScalaVersion
3730

3831
override def scalacOptions = super.scalacOptions() ++
3932
Agg("-language:reflectiveCalls", "-Ymacro-annotations", "-Ytasty-reader")
@@ -48,9 +41,9 @@ object rocketchip extends `rocket-chip`.common.RocketChipModule with HasChisel {
4841
val rcPath = os.pwd / "rocket-chip"
4942
override def millSourcePath = rcPath
5043

51-
def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0"
44+
def mainargsIvy = ivy"com.lihaoyi::mainargs:0.7.0"
5245

53-
def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5"
46+
def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.7"
5447

5548
object macros extends `rocket-chip`.common.MacrosModule with HasChisel {
5649
def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${scalaVersion}"
@@ -97,7 +90,10 @@ object CoupledL2 extends SbtModule with HasChisel with millbuild.common.CoupledL
9790

9891
object test extends SbtModuleTests with TestModule.ScalaTest {
9992
override def ivyDeps = super.ivyDeps() ++ Agg(
100-
getVersion("chiseltest"),
93+
defaultVersions("chiseltest"),
10194
)
10295
}
96+
97+
override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
98+
10399
}

‎rocket-chip

‎src/main/scala/coupledL2/CoupledL2.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -213,8 +213,8 @@ trait HasCoupledL2Parameters {
213213
}
214214

215215
def sizeBytesToStr(sizeBytes: Double): String = sizeBytes match {
216-
case _ if sizeBytes >= 1024 * 1024 => (sizeBytes / 1024 / 1024) + "MB"
217-
case _ if sizeBytes >= 1024 => (sizeBytes / 1024) + "KB"
216+
case _ if sizeBytes >= 1024 * 1024 => s"${sizeBytes / 1024 / 1024}MB"
217+
case _ if sizeBytes >= 1024 => s"${sizeBytes / 1024}KB"
218218
case _ => "B"
219219
}
220220

‎src/main/scala/coupledL2/utils/CustomAnnotations.scala

Lines changed: 0 additions & 46 deletions
This file was deleted.

‎src/main/scala/coupledL2/utils/Queue_SRAM.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ object Queue_SRAM {
167167
enq.ready := deq.ready
168168
deq
169169
} else {
170-
val q = Module(new Queue_SRAM(chiselTypeOf(enq.bits), entries, pipe, flow, useSyncReadMem, flush.isDefined))
170+
val q = Module(new Queue_SRAM(chiselTypeOf(enq.bits), entries, pipe, flow, useSyncReadMem, flush.isDefined)())
171171
q.io.flush.zip(flush).foreach(f => f._1 := f._2)
172172
q.io.enq.valid := enq.valid // not using <> so that override is allowed
173173
q.io.enq.bits := enq.bits

‎src/main/scala/coupledL2/utils/SRAMTemplate.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ package coupledL2.utils
2323
import chisel3._
2424
import chisel3.util._
2525
import freechips.rocketchip.tilelink.LFSR64
26+
import huancun.utils.CustomAnnotations
2627

2728
object HoldUnless {
2829
def apply[T <: Data](x: T, en: Bool): T = Mux(en, x, RegEnable(x, 0.U.asTypeOf(x), en))

‎src/test/scala/TestProbeQueue.scala

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,10 @@ import freechips.rocketchip.diplomacy.LazyModule
55

66

77
import chisel3._
8+
import circt.stage.ChiselStage
89
import chisel3.util._
910
import org.chipsalliance.cde.config._
10-
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
11+
import chisel3.stage.ChiselGeneratorAnnotation
1112
import freechips.rocketchip.diplomacy._
1213
import freechips.rocketchip.tilelink._
1314
import scala.collection.mutable.ArrayBuffer
@@ -25,14 +26,14 @@ object TestProbeQueue extends App {
2526
})
2627

2728
val top_coupledl2 = DisableMonitors(p => LazyModule(new TestTop_L2()(p)) )(config)
28-
chisel3.stage.ChiselStage.elaborate(top_coupledl2.module)
29+
ChiselStage.convert(top_coupledl2.module)
2930

3031
val arb_args = chisel3.aop.Select.collectDeep[ProbeQueue](top_coupledl2.module){
3132
case ds: ProbeQueue =>
3233
ds
3334
}.head
3435

35-
(new chisel3.stage.ChiselStage).emitVerilog(new ProbeQueue()(arb_args.p))
36+
ChiselStage.emitSystemVerilog(new ProbeQueue()(arb_args.p))
3637
}
3738

3839

‎src/test/scala/TestSplittedSRAM.scala

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ import chiseltest.RawTester.test
88
import chisel3.experimental._
99
import chisel3.testers._
1010
import org.chipsalliance.cde.config._
11-
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
1211
import scala.collection.mutable.ArrayBuffer
1312
import chiseltest.WriteVcdAnnotation
1413
import scala.util.Random

‎src/test/scala/TestTop.scala

Lines changed: 26 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
package coupledL2
22

33
import chisel3._
4+
import circt.stage.{ChiselStage, FirtoolOption}
45
import chisel3.util._
56
import org.chipsalliance.cde.config._
6-
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
7+
import chisel3.stage.ChiselGeneratorAnnotation
78
import freechips.rocketchip.diplomacy._
89
import freechips.rocketchip.tile.MaxHartIdBits
910
import freechips.rocketchip.tilelink._
@@ -655,6 +656,15 @@ class TestTop_fullSys()(implicit p: Parameters) extends LazyModule {
655656
}
656657
}
657658

659+
private[coupledL2] object TestTopFirtoolOptions {
660+
def apply() = Seq(
661+
FirtoolOption("--disable-annotation-unknown"),
662+
FirtoolOption("--repl-seq-mem"),
663+
FirtoolOption("--repl-seq-mem-file=TestTop.sv.conf"),
664+
FirtoolOption("--lowering-options=explicitBitcast")
665+
)
666+
}
667+
658668
object TestTop_L2 extends App {
659669
val config = baseConfig(1).alterPartial({
660670
case L2ParamKey => L2Param(
@@ -665,9 +675,9 @@ object TestTop_L2 extends App {
665675
ChiselDB.init(false)
666676

667677
val top = DisableMonitors(p => LazyModule(new TestTop_L2()(p)) )(config)
668-
(new ChiselStage).execute(args, Seq(
669-
ChiselGeneratorAnnotation(() => top.module)
670-
))
678+
(new ChiselStage).execute(args,
679+
ChiselGeneratorAnnotation(() => top.module) +: TestTopFirtoolOptions()
680+
)
671681

672682
ChiselDB.addToFileRegisters
673683
FileRegisters.write("./build")
@@ -683,9 +693,9 @@ object TestTop_L2_Standalone extends App {
683693
ChiselDB.init(false)
684694

685695
val top = DisableMonitors(p => LazyModule(new TestTop_L2_Standalone()(p)) )(config)
686-
(new ChiselStage).execute(args, Seq(
687-
ChiselGeneratorAnnotation(() => top.module)
688-
))
696+
(new ChiselStage).execute(args,
697+
ChiselGeneratorAnnotation(() => top.module) +: TestTopFirtoolOptions()
698+
)
689699

690700
ChiselDB.addToFileRegisters
691701
FileRegisters.write("./build")
@@ -705,9 +715,9 @@ object TestTop_L2L3 extends App {
705715
Constantin.init(false)
706716

707717
val top = DisableMonitors(p => LazyModule(new TestTop_L2L3()(p)) )(config)
708-
(new ChiselStage).execute(args, Seq(
709-
ChiselGeneratorAnnotation(() => top.module)
710-
))
718+
(new ChiselStage).execute(args,
719+
ChiselGeneratorAnnotation(() => top.module) +: TestTopFirtoolOptions()
720+
)
711721

712722
ChiselDB.addToFileRegisters
713723
Constantin.addToFileRegisters
@@ -728,9 +738,9 @@ object TestTop_L2L3L2 extends App {
728738
Constantin.init(false)
729739

730740
val top = DisableMonitors(p => LazyModule(new TestTop_L2L3L2()(p)))(config)
731-
(new ChiselStage).execute(args, Seq(
732-
ChiselGeneratorAnnotation(() => top.module)
733-
))
741+
(new ChiselStage).execute(args,
742+
ChiselGeneratorAnnotation(() => top.module) +: TestTopFirtoolOptions()
743+
)
734744

735745
ChiselDB.addToFileRegisters
736746
Constantin.addToFileRegisters
@@ -750,9 +760,9 @@ object TestTop_fullSys extends App {
750760
ChiselDB.init(false)
751761

752762
val top = DisableMonitors(p => LazyModule(new TestTop_fullSys()(p)))(config)
753-
(new ChiselStage).execute(args, Seq(
754-
ChiselGeneratorAnnotation(() => top.module)
755-
))
763+
(new ChiselStage).execute(args,
764+
ChiselGeneratorAnnotation(() => top.module) +: TestTopFirtoolOptions()
765+
)
756766

757767
ChiselDB.addToFileRegisters
758768
FileRegisters.write("./build")

‎src/test/scala/TestWritebackQueue.scala

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@ import freechips.rocketchip.diplomacy.LazyModule
77
import chisel3._
88
import chisel3.util._
99
import org.chipsalliance.cde.config._
10-
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
1110
import freechips.rocketchip.diplomacy._
1211
import freechips.rocketchip.tilelink._
1312
import scala.collection.mutable.ArrayBuffer

‎src/test/scala/chi/TestTop.scala

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
package coupledL2
22

33
import chisel3._
4+
import circt.stage.ChiselStage
45
import chisel3.util._
56
import org.chipsalliance.cde.config._
6-
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
7+
import chisel3.stage.ChiselGeneratorAnnotation
78
import freechips.rocketchip.diplomacy._
89
import freechips.rocketchip.tilelink._
910
import freechips.rocketchip.tile.MaxHartIdBits
@@ -222,9 +223,9 @@ object TestTopCHIHelper {
222223

223224
val top = DisableMonitors(p => LazyModule(fTop(p)))(config)
224225

225-
(new ChiselStage).execute(args, Seq(
226-
ChiselGeneratorAnnotation(() => top.module)
227-
))
226+
(new ChiselStage).execute(args,
227+
ChiselGeneratorAnnotation(() => top.module) +: TestTopFirtoolOptions()
228+
)
228229

229230
ChiselDB.addToFileRegisters
230231
FileRegisters.write("./build")
@@ -253,7 +254,7 @@ Usage: TestTop_CHIL2 [<--option> <values>]
253254
System.exit(-1)
254255
}
255256

256-
var varArgs = ArrayBuffer(args:_*)
257+
var varArgs = ArrayBuffer(args.toIndexedSeq:_*)
257258
var varArgsDropped = 0
258259

259260
var numCores: Int = 2
@@ -280,7 +281,7 @@ Usage: TestTop_CHIL2 [<--option> <values>]
280281
varArgs.remove(i - varArgsDropped, 2)
281282
varArgsDropped = varArgsDropped + 2
282283
})
283-
varArgs.trimToSize
284+
varArgs.trimToSize()
284285

285286
TestTopCHIHelper.gen(
286287
p => new TestTop_CHIL2(

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