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MSHRCtl: change P-credit arbiter from Round-Robin to Random #142

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May 6, 2024
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MSHRCtl: change P-credit arbiter from Round-Robin to Random #142

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21 changes: 18 additions & 3 deletions src/main/scala/coupledL2/tl2chi/MSHRCtl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ package coupledL2.tl2chi

import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import utility._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._
Expand Down Expand Up @@ -127,23 +128,37 @@ class MSHRCtl(implicit p: Parameters) extends TL2CHIL2Module {
*/
val isPCrdGrant = io.resps.rxrsp.valid && (io.resps.rxrsp.respInfo.chiOpcode.get === PCrdGrant)
val waitPCrdInfo = Wire(Vec(mshrsAll, new PCrdInfo))
val pArb = Module(new RRArbiter(UInt(), mshrsAll))
// val pArb = Module(new RRArbiter(UInt(), mshrsAll))

val matchPCrdGrant = VecInit(waitPCrdInfo.map(p =>
isPCrdGrant && p.valid &&
p.srcID.get === io.resps.rxrsp.respInfo.srcID.get &&
p.pCrdType.get === io.resps.rxrsp.respInfo.pCrdType.get
))

pArb.io.in.zipWithIndex.foreach {
/* pArb.io.in.zipWithIndex.foreach {
case (in, i) =>
in.valid := matchPCrdGrant(i)
in.bits := 0.U
}
pArb.io.out.ready := true.B
val pCrdRR = VecInit(UIntToOH(pArb.io.chosen))
val pCrdPri = VecInit((matchPCrdGrant.asUInt & pCrdRR.asUInt).asBools)
// val pCrdPri = VecInit(PriorityEncoderOH(matchPCrdGrant))
//val pCrdPri = VecInit(PriorityEncoderOH(matchPCrdGrant))
val pCrdIsWait = OHToUInt(pCrdPri)
*/

/*
Random arbiter if multi-entry match
*/
val lfsr = LFSR(16, true.B)
val idx = Random(16, lfsr)
val idxOH = VecInit(UIntToOH(idx))

val doubleReq = Fill(2, matchPCrdGrant.asUInt)
val doubleGnt = ~(doubleReq - idxOH.asUInt) & doubleReq
val gnt = doubleGnt(31,16) | doubleGnt(15,0)
val pCrdPri = VecInit(gnt.asBools)
val pCrdIsWait = OHToUInt(pCrdPri)

/* when PCrdGrant come before RetryAck, 16 entry CAM used to:
Expand Down
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