Merge branch 'master' into chi-coupledl2 #144
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* SinkC: fix bug for regs Buf not init * MSHR: fix bug when L1_acquirePerm but L2_miss, L2 should acquireBlock to L3, not only acquirePerm * MainPipe: when L3_probetoB and L2=TIP, L2 donot need probetoB L1 * SinkB: cannot accept Probe when same-addr Release to L3 and have not receive ReleaseAck --------- Co-authored-by: Cai Luoshan <[email protected]>
* ReqArb: only give s1 info when s1-to-s2 fire * Backbone: new structure for Hint now we send Hint @s1 for every MSHR-GrantData passing by and send Hint @s3 for every CHN-GrantData passing by * CoupledL2: update logic for Hint Arb * misc: fix connection * Hint: consider new feature ** AMergeTask ** * Hint: fix Hint Arb among Slices * Hint: add keyword info
…try, instead of refillRetry (#103) Co-authored-by: Cai Luoshan <[email protected]>
* configs: use hartid from io Using hartid from parameters will result in the module not being deduplicated by chisel and firrtl. Each hart will produce its module in verilog, making it hard for the rtl simulator to optimize. Signed-off-by: Yangyu Chen <[email protected]> * huancun: bump huancun Signed-off-by: Yangyu Chen <[email protected]> --------- Signed-off-by: Yangyu Chen <[email protected]>
* configs: fix use hartid from io (#102) I have written 'tp.io.hartid := tpio.tpmeta_port.get.req.bits.hartid' before in #103. However, it is not the hartid that comes from tile but TemporalPrefetcher and caused a loop in Chisel.Queue, as it doesn't use flow, so we didn't see errors in FIRRTL but we will not get the right hartId. This commit fixes this by adding an io to the CoupledL2 module and using hartId input from the L2Top module. To get this done, we must modify L2Top.scala like this outside this repo. ```diff diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala index b4865aba5..07d1668bb 100644 --- a/src/main/scala/xiangshan/L2Top.scala +++ b/src/main/scala/xiangshan/L2Top.scala @@ -144,6 +144,7 @@ class L2Top()(implicit p: Parameters) extends LazyModule if (l2cache.isDefined) { l2_hint := l2cache.get.module.io.l2_hint // debugTopDown <> l2cache.get.module.io.debugTopDown + l2cache.get.module.io.hartId := hartId.fromTile l2cache.get.module.io.debugTopDown.robHeadPaddr := DontCare l2cache.get.module.io.debugTopDown.robHeadPaddr.head := debugTopDown.robHeadPaddr debugTopDown.l2MissMatch := l2cache.get.module.io.debugTopDown.l2MissMatch.head ``` Finally, this commit also adds DontCare for this new signal to TestTop.scala. Signed-off-by: Yangyu Chen <[email protected]> * testtop: fix unconnected signals Signed-off-by: Yangyu Chen <[email protected]> --------- Signed-off-by: Yangyu Chen <[email protected]>
* misc: fix compiling issue concerning vaddr * bop: change to virtual address space training * l2 bop: catch the empty signals * l2 bop: change to pipeline form and fix bug * l2 bop: fix request vaddr transfer * l2 bop: add prefetch req filter * l2 bop: fix bug of more prefetch requests * l2 bop: close constantin control initially * l2 bop: fix bug of chiseldb * l2 bop: fix bug of chiseldb * l2bop: change filter and fill invalid entry preferentially * l2-bop: add req buffer and tlb replay count * l2bop-fix bug of wire connection * l2bop: fix bug of wire connection * l2bop: add replayEn and drop logic * Prefetch: L2 BOP pftReq-Hit does not response to Prefetcher * common: delete unused signals * coupled2: set default io signals assignment * bop: fix tlb excp signal bug * bop: avoid uncertain memory access training * bop: remove fire() * bop: set double replay * bop: add bop train record db * bop: fix alloc bug * Revert "bop: set double replay" This reverts commit ba65569. * bop: use both vbop and pbop * prefetch: add pfSource of resp * bop: fix bug of resp source label * prefetch: add flag PBOP * prefetch: add pbop record * bop: add dynamic diable * bop: badscore is controlled by constantin * notmerge-l2bop: upd topdown * notmerge-l2bop: add constantin badscore and rolling by commitInstr * bop: baseline of pvbop-02 * bop: add pbop CrossPage * bop: add offset 117,147,91 on pcp * prefetch: add delay queue * l2bop: fix compile bug in minimal config * bump: utility * bop: fix compile bug * testtop: fix test bug --------- Co-authored-by: wangkaifan <[email protected]> Co-authored-by: XiChen <[email protected]>
Kumonda221-CrO3
approved these changes
May 7, 2024
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