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configs: use single hartid #147

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May 12, 2024
Merged

configs: use single hartid #147

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d9af6b4
configs: use single hartid
cyyself May 11, 2024
b6b0147
Bump HuanCun
cyyself May 11, 2024
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2 changes: 1 addition & 1 deletion HuanCun
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Submodule HuanCun updated 5 files
+1 −1 Utility
+0 −34 src/main/resources/STD_CLKGT_func.v
+2 −6 src/main/scala/huancun/BaseDirectory.scala
+3 −2 src/main/scala/huancun/HuanCun.scala
+2 −16 src/main/scala/huancun/utils/SRAMWrapper.scala
9 changes: 5 additions & 4 deletions src/main/scala/coupledL2/CoupledL2.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ import chisel3._
import chisel3.util._
import utility.{FastArbiter, ParallelMax, ParallelPriorityMux, Pipeline, RegNextN}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tilelink.TLMessages._
import freechips.rocketchip.util._
Expand Down Expand Up @@ -83,7 +84,7 @@ trait HasCoupledL2Parameters {
lazy val msgSizeBits = edgeIn.bundle.sizeBits
lazy val sourceIdAll = 1 << sourceIdBits

lazy val hartIdLen: Int = log2Up(cacheParams.hartIds.length)
lazy val hartIdLen: Int = p(MaxHartIdBits)

val mshrsAll = cacheParams.mshrs
val idsAll = 256// ids of L2 //TODO: Paramterize like this: max(mshrsAll * 2, sourceIdAll * 2)
Expand Down Expand Up @@ -247,8 +248,8 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
val l2_tlb_req = new L2ToL1TlbIO(nRespDups = 1)(l2TlbParams)
val debugTopDown = new Bundle {
val robTrueCommit = Input(UInt(64.W))
val robHeadPaddr = Vec(cacheParams.hartIds.length, Flipped(Valid(UInt(36.W))))
val l2MissMatch = Vec(cacheParams.hartIds.length, Output(Bool()))
val robHeadPaddr = Flipped(Valid(UInt(36.W)))
val l2MissMatch = Output(Bool())
}
})

Expand Down Expand Up @@ -465,7 +466,7 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
case (in, s) => in := s.io.latePF.get
}
t.io.debugTopDown <> io.debugTopDown
case None => io.debugTopDown.l2MissMatch.foreach(_ := false.B)
case None => io.debugTopDown.l2MissMatch := false.B
}

// ==================== XSPerf Counters ====================
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/coupledL2/L2Param.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ case class L2Param
e = BufferParams.default
),

hartIds: Seq[Int] = Seq[Int](),
hartId: Int = 0,
// Prefetch
prefetch: Option[PrefetchParameters] = None,
// Performance analysis
Expand Down
32 changes: 15 additions & 17 deletions src/main/scala/coupledL2/TopDownMonitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -31,32 +31,30 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
val latePF = Vec(banks, Input(Bool()))
val debugTopDown = new Bundle {
val robTrueCommit = Input(UInt(64.W))
val robHeadPaddr = Vec(cacheParams.hartIds.length, Flipped(Valid(UInt(36.W))))
val l2MissMatch = Vec(cacheParams.hartIds.length, Output(Bool()))
val robHeadPaddr = Flipped(Valid(UInt(36.W)))
val l2MissMatch = Output(Bool())
}
})

/* ====== PART ONE ======
* Check whether the Addr given by core is a Miss in Cache
*/
for (((hartId, pAddr), addrMatch) <- cacheParams.hartIds zip io.debugTopDown.robHeadPaddr zip io.debugTopDown.l2MissMatch) {
val addrMatchVec = io.msStatus.zipWithIndex.map {
case(slice, i) =>
slice.map {
ms =>
val msBlockAddr = if(bankBits == 0) Cat(ms.bits.reqTag, ms.bits.set)
else Cat(ms.bits.reqTag, ms.bits.set, i.U(bankBits-1, 0))
val pBlockAddr = (pAddr.bits >> 6.U).asUInt
val isMiss = ms.valid && ms.bits.is_miss
val addrMatchVec = io.msStatus.zipWithIndex.map {
case(slice, i) =>
slice.map {
ms =>
val msBlockAddr = if(bankBits == 0) Cat(ms.bits.reqTag, ms.bits.set)
else Cat(ms.bits.reqTag, ms.bits.set, i.U(bankBits-1, 0))
val pBlockAddr = (io.debugTopDown.robHeadPaddr.bits >> 6.U).asUInt
val isMiss = ms.valid && ms.bits.is_miss

pAddr.valid && (msBlockAddr === pBlockAddr) && isMiss
}
}

addrMatch := Cat(addrMatchVec.flatten).orR
XSPerfAccumulate(cacheParams, s"${cacheParams.name}MissMatch_${hartId}", addrMatch)
io.debugTopDown.robHeadPaddr.valid && (msBlockAddr === pBlockAddr) && isMiss
}
}

io.debugTopDown.l2MissMatch := Cat(addrMatchVec.flatten).orR
XSPerfAccumulate(cacheParams, s"${cacheParams.name}MissMatch_${cacheParams.hartId}", io.debugTopDown.l2MissMatch)

/* ====== PART TWO ======
* Count the parallel misses, and divide them into CPU/Prefetch
*/
Expand Down
3 changes: 1 addition & 2 deletions src/main/scala/coupledL2/debug/Monitor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -85,9 +85,8 @@ class Monitor(implicit p: Parameters) extends L2Module {


/* ======== ChiselDB ======== */
// assert(cacheParams.hartIds.length == 1, "private L2 should have one and only one hardId")
if (cacheParams.enableMonitor && !cacheParams.FPGAPlatform) {
val hartId = if (cacheParams.hartIds.length == 1) cacheParams.hartIds.head else 0
val hartId = cacheParams.hartId
val table = ChiselDB.createTable(s"L2MP", new CPL2S3Info, basicDB = true)
val s3Info = Wire(new CPL2S3Info)
s3Info.mshrTask := req_s3.mshrTask
Expand Down
3 changes: 1 addition & 2 deletions src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -137,8 +137,7 @@ class TemporalPrefetch(implicit p: Parameters) extends TPModule {

/* Constantin Parameters */

require(cacheParams.hartIds.size == 1)
val hartid = cacheParams.hartIds.head
val hartid = cacheParams.hartId
// 0 / 1: whether to enable temporal prefetcher
private val enableTP = Constantin.createRecord("enableTP"+hartid.toString, initValue = 1)
// 0 ~ N: throttle cycles for each prefetch request
Expand Down
33 changes: 21 additions & 12 deletions src/test/scala/TestTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ import chisel3.util._
import org.chipsalliance.cde.config._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink._
import huancun._
import coupledL2.prefetch._
Expand All @@ -13,6 +14,14 @@ import utility.{ChiselDB, FileRegisters, TLLogger}

import scala.collection.mutable.ArrayBuffer

object baseConfig {
def apply(maxHartIdBits: Int) = {
new Config((_, _, _) => {
case MaxHartIdBits => maxHartIdBits
})
}
}

class TestTop_L2()(implicit p: Parameters) extends LazyModule {

/* L1D
Expand Down Expand Up @@ -126,7 +135,7 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
))
val master_nodes = Seq(l1d, l1i)

val l2 = LazyModule(new CoupledL2()(new Config((_, _, _) => {
val l2 = LazyModule(new CoupledL2()(baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
name = s"l2",
ways = 4,
Expand All @@ -140,7 +149,7 @@ class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
)
})))

val l3 = LazyModule(new HuanCun()(new Config((_, _, _) => {
val l3 = LazyModule(new HuanCun()(baseConfig(1).alterPartial({
case HCCacheParamsKey => HCCacheParameters(
name = "l3",
level = 3,
Expand Down Expand Up @@ -328,19 +337,19 @@ class TestTop_L2L3L2()(implicit p: Parameters) extends LazyModule {
val l1d_nodes = (0 until nrL2).map(i => createClientNode(s"l1d$i", 32))
val master_nodes = l1d_nodes

val coupledL2 = (0 until nrL2).map(i => LazyModule(new CoupledL2()(new Config((_, _, _) => {
val coupledL2 = (0 until nrL2).map(i => LazyModule(new CoupledL2()(baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
name = s"l2$i",
ways = 4,
sets = 128,
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
echoField = Seq(DirtyField()),
hartIds = Seq{i}
hartId = i
)
}))))
val l2_nodes = coupledL2.map(_.node)

val l3 = LazyModule(new HuanCun()(new Config((_, _, _) => {
val l3 = LazyModule(new HuanCun()(baseConfig(1).alterPartial({
case HCCacheParamsKey => HCCacheParameters(
name = "L3",
level = 3,
Expand Down Expand Up @@ -457,7 +466,7 @@ class TestTop_fullSys()(implicit p: Parameters) extends LazyModule {
master_nodes = master_nodes ++ Seq(l1d, l1i) // TODO

val l1xbar = TLXbar()
val l2 = LazyModule(new CoupledL2()(new Config((_, _, _) => {
val l2 = LazyModule(new CoupledL2()(baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
name = s"l2$i",
ways = 4,
Expand All @@ -481,7 +490,7 @@ class TestTop_fullSys()(implicit p: Parameters) extends LazyModule {
}
}

val l3 = LazyModule(new HuanCun()(new Config((_, _, _) => {
val l3 = LazyModule(new HuanCun()(baseConfig(1).alterPartial({
case HCCacheParamsKey => HCCacheParameters(
name = "L3",
level = 3,
Expand Down Expand Up @@ -527,7 +536,7 @@ class TestTop_fullSys()(implicit p: Parameters) extends LazyModule {
}

object TestTop_L2 extends App {
val config = new Config((_, _, _) => {
val config = baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
echoField = Seq(DirtyField())
Expand All @@ -545,7 +554,7 @@ object TestTop_L2 extends App {
}

object TestTop_L2_Standalone extends App {
val config = new Config((_, _, _) => {
val config = baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
echoField = Seq(DirtyField())
Expand All @@ -563,7 +572,7 @@ object TestTop_L2_Standalone extends App {
}

object TestTop_L2L3 extends App {
val config = new Config((_, _, _) => {
val config = baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
echoField = Seq(DirtyField())
Expand All @@ -584,7 +593,7 @@ object TestTop_L2L3 extends App {
}

object TestTop_L2L3L2 extends App {
val config = new Config((_, _, _) => {
val config = baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
// echoField = Seq(DirtyField())
Expand All @@ -605,7 +614,7 @@ object TestTop_L2L3L2 extends App {
}

object TestTop_fullSys extends App {
val config = new Config((_, _, _) => {
val config = baseConfig(1).alterPartial({
case L2ParamKey => L2Param(
clientCaches = Seq(L1Param(aliasBitsOpt = Some(2))),
echoField = Seq(DirtyField())
Expand Down
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