GrantBuffer: Modify assert 'inflightGrant entries should not be full'…#154
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Archer613 wants to merge 5 commits intoOpenXiangShan:chi-coupledl2from
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GrantBuffer: Modify assert 'inflightGrant entries should not be full'…#154Archer613 wants to merge 5 commits intoOpenXiangShan:chi-coupledl2from
Archer613 wants to merge 5 commits intoOpenXiangShan:chi-coupledl2from
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The hartid can be found in what `%m` displays.
This pull request introduces TL2CHICoupledL2, which adopts TileLink standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification to connect downstream interconnect. The key features of TL2CHICoupledL2 are: Fully coherent Request Node in a CHI interconnect. Coherency granule of 64B cache line. MESI cache coherence model, which is based on TileLink coherence policies. Transition from TL-C transactions to CHI snoopable requests. Transition from TL-UL transactions to CHI non-snoopable requests. Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique. Support for WriteNoSnp, WriteBackFull, Evict. Support for all the snoops except for SnpDVMOp. Request retry to manage protocol resources. Message transfer across CHI interfaces based on Link Layer Credit. Power aware signaling on the component interface. The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2 still works as default L2 Cache instance in XiangShan processor for now. However, you can switch to TL2CHICoupledL2 by setting EnableCHI Field to true in src/test/scala/chi/TestTop.scala. --------- Co-authored-by: Zhu Yu <[email protected]> Co-authored-by: Chen Xi <[email protected]> Co-authored-by: Kumonda221 <[email protected]> Co-authored-by: cyril0124 <[email protected]>
…n#152) A transaction size of up to 16-byte is always contained in a single packet. The DataID field value must be set to Addr[5:4] because the DataID field represents Addr[5:4] of the lowest addressed byte within the packet. Co-authored-by: zhanglinjuan <[email protected]>
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… -> 'inflightGrant entries overflow'