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RXSNP: add pipeline to ease timing for rxsnp logics #158

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merged 2 commits into from
May 20, 2024
Merged

RXSNP: add pipeline to ease timing for rxsnp logics #158

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1a59712
Directory: fix overloaded method of fire when MFC=1
linjuanZ May 15, 2024
00c8dd3
RXSNP: add pipeline to ease timing for rxsnp logics
linjuanZ May 15, 2024
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4 changes: 2 additions & 2 deletions src/main/scala/coupledL2/Directory.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -283,9 +283,9 @@ class Directory(implicit p: Parameters) extends L2Module {
// origin-bit marks whether the data_block is reused
val origin_bit_opt = if(random_repl) None else
Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true)))
val origin_bits_r = origin_bit_opt.get.io.r(io.read.fire(), io.read.bits.set).resp.data
val origin_bits_r = origin_bit_opt.get.io.r(io.read.fire, io.read.bits.set).resp.data
val origin_bits_hold = Wire(Vec(ways, Bool()))
origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire(), false.B))
origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire, false.B))
origin_bit_opt.get.io.w(
replacerWen,
rrip_hit_s3,
Expand Down
18 changes: 11 additions & 7 deletions src/main/scala/coupledL2/tl2chi/RXSNP.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,10 @@ class RXSNP(
val msInfo = Vec(mshrsAll, Flipped(ValidIO(new MSHRInfo())))
})

val rxsnp = Wire(io.rxsnp.cloneType)
val queue = Module(new Queue(io.rxsnp.bits.cloneType, 2, flow = false))
rxsnp <> queue.io.deq
queue.io.enq <> io.rxsnp
val task = Wire(new TaskBundle)

/**
Expand Down Expand Up @@ -75,24 +79,24 @@ class RXSNP(
)).asUInt
val replaceDataMask = VecInit(io.msInfo.map(_.bits.replaceData)).asUInt

task := fromSnpToTaskBundle(io.rxsnp.bits)
task := fromSnpToTaskBundle(rxsnp.bits)

val stall = reqBlockSnp || replaceBlockSnp // addrConflict || replaceConflict
io.task.valid := io.rxsnp.valid && !stall
io.task.valid := rxsnp.valid && !stall
io.task.bits := task
io.rxsnp.ready := io.task.ready && !stall
rxsnp.ready := io.task.ready && !stall

val stallCnt = RegInit(0.U(64.W))
when(io.rxsnp.fire) {
when(rxsnp.fire) {
stallCnt := 0.U
}.elsewhen(io.rxsnp.valid && !io.rxsnp.ready) {
}.elsewhen(rxsnp.valid && !rxsnp.ready) {
stallCnt := stallCnt + 1.U
}

val STALL_CNT_MAX = 28000.U
assert(stallCnt <= STALL_CNT_MAX, "stallCnt full! maybe there is a deadlock! addr => 0x%x req_opcode => %d txn_id => %d", io.rxsnp.bits.addr, io.rxsnp.bits.opcode, io.rxsnp.bits.txnID);
assert(stallCnt <= STALL_CNT_MAX, "stallCnt full! maybe there is a deadlock! addr => 0x%x req_opcode => %d txn_id => %d", rxsnp.bits.addr, rxsnp.bits.opcode, rxsnp.bits.txnID);

assert(!(stall && io.rxsnp.fire))
assert(!(stall && rxsnp.fire))

def fromSnpToTaskBundle(snp: CHISNP): TaskBundle = {
val task = WireInit(0.U.asTypeOf(new TaskBundle))
Expand Down
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