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Directory: fixed X-state leakage from RRIP meta SRAM without reset #163

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merged 2 commits into from
May 21, 2024
Merged

Directory: fixed X-state leakage from RRIP meta SRAM without reset #163

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5ce09ac
Directory: fixed X-state leakage from RRIP meta SRAM without reset
Kumonda221-CrO3 May 20, 2024
576c822
.github: update CODEOWNERS
linjuanZ May 21, 2024
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4 changes: 2 additions & 2 deletions .github/CODEOWNERS
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
* @Ivyfeather @linjuanZ
src/main/scala/coupledL2/Directory.scala @cailuoshan
src/main/scala/coupledL2/utils/ @cailuoshan
src/main/scala/coupledL2/Directory.scala @cailuoshan @linjuanZ
src/main/scala/coupledL2/utils/ @cailuoshan @linjuanZ
src/main/scala/coupledL2/prefetch/ @Maxpicca-Li
src/main/scala/coupledL2/prefetch/ @wakafa1
src/test/scala/ @Kumonda221-CrO3
8 changes: 4 additions & 4 deletions src/main/scala/coupledL2/Directory.scala
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Expand Up @@ -282,14 +282,14 @@ class Directory(implicit p: Parameters) extends L2Module {
val rrip_hit_s3 = Mux(refillReqValid_s3, false.B, hit_s3)
// origin-bit marks whether the data_block is reused
val origin_bit_opt = if(random_repl) None else
Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true)))
Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true, shouldReset = true)))
val origin_bits_r = origin_bit_opt.get.io.r(io.read.fire, io.read.bits.set).resp.data
val origin_bits_hold = Wire(Vec(ways, Bool()))
origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire, false.B))
origin_bit_opt.get.io.w(
replacerWen,
rrip_hit_s3,
req_s3.set,
!resetFinish || replacerWen,
Mux(resetFinish, rrip_hit_s3, false.B),
Mux(resetFinish, req_s3.set, resetIdx),
UIntToOH(touch_way_s3)
)

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