feat(topdown): add the source output of late prefetch#411
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Squashed commit of the following: commit c4550b1 Author: Yanqin Li <[email protected]> Date: Thu Oct 16 22:48:02 2025 +0800 feat(pf): add csr control of delay latency for l2 prefetch train (#434) commit 72416c4 Author: Yanqin Li <[email protected]> Date: Thu Oct 16 22:47:46 2025 +0800 feat(topdown): add the srouce output of late prefetch (#411) commit b754686 Author: Ma-YX <[email protected]> Date: Sun Sep 28 17:43:16 2025 +0800 Area(DataStorage): change Data SRAM's split to 4 (#432) Given the new physical-design backend requirements, changing the L2 Data SRAM specification to split = 4 is more favorable for both timing and area. commit abf2f74 Author: Tang Haojin <[email protected]> Date: Thu Sep 18 17:14:51 2025 +0800 build: bump chisel 7 and keep compatible with 6.7.0 (#431) commit 8c7dab9 Author: zhaohong1988 <[email protected]> Date: Fri Sep 5 16:41:03 2025 +0800 feat(MMIOBridge): exclude clint range inner xstilewrap to map the new clint ip (#429) commit 4a150c0 Author: Ding Haonan <[email protected]> Date: Mon Sep 1 13:14:22 2025 +0800 chore(TestTop): embedded CLog.B recording for CHI TestTop (#410) * submodule(utility): bump utility commit 5a610b4 Author: zhanglinjuan <[email protected]> Date: Wed Jul 16 11:30:49 2025 +0800 fix(MSHR): fix X-state propagation from RefillBuf (#426) For an MSHR entry handling AcquirePerm, the data in the corresponding RefillBuf is invalid. When the MSHR entry performs a replacement, it needs to write data in RefillBuf into DS, and the write enable signal `dsWen` of replacement request is always driven HIGH. This results in writing X-state data into DS. Although this theoretically does not cause bugs, it will trigger assertion in MCP2 check. commit d5f5c41 Author: Ding Haonan <[email protected]> Date: Fri Jul 11 18:42:24 2025 +0800 fix(Common, MSHR, MMIOBridge): reserve max QoS for real-time devices (#423) * Take ```MAX_QOS - 1``` for all CPU requests. commit 94f5f61 Author: yulightenyu <[email protected]> Date: Fri Jul 4 13:50:32 2025 +0800 fix(LinkLayer): fix exitcoDone signal right after reset (#424) * fix(Linklayer): fix exitcoDone singal right after reset This fix try to fix the false active of 'exitcoDone' the cycle after reset release. So as to resolve the CHI protocal 13.7.2: TXSACTIVE must be asserted when SYSCOREQ is high. * use && for single bit logic commit 5ab646e Author: yulightenyu <[email protected]> Date: Tue Jun 24 13:01:00 2025 +0800 fix(LinkLayer): fix linkactive time when power down (#422) when RN want to exit coherency (syscoreq=0), linkactive should NOT be deasserted before syscoack=0 indicating there is pending snoop on the way, so tx linkactive should keep active until syscozck==0 commit 70fe66f Author: yulightenyu <[email protected]> Date: Tue Jun 24 13:00:37 2025 +0800 fix(Linklayer): fix txsactive asserted before syscoreq after reset (#420) commit d0f0bd6 Author: Ding Haonan <[email protected]> Date: Tue Jun 17 13:52:31 2025 +0800 fix(MSHR): EWA always asserts on cacheable (revert #417) (#419) commit 9c1d363 Author: Ding Haonan <[email protected]> Date: Fri Jun 13 01:57:03 2025 +0800 fix(RequesterArb, MSHR): cancel replace task on read NDERR (#418) * fix(RequesterArb, MSHR): cancel replace task on read NDERR Co-authored-by: Ma-YX <[email protected]> commit 5a158eb Author: Ding Haonan <[email protected]> Date: Wed Jun 11 17:38:35 2025 +0800 fix(MSHR): deassert EWA for CMO transactions (#417) * To meet ISA specification, CMO instructions should only be returned after the consequence was visible to all **non-coherent** agents, which might be out of the CHI domain (e.g. DMAs on crossbars near to memory controller). commit 800bb00 Author: yulightenyu <[email protected]> Date: Sun Jun 1 17:10:16 2025 +0800 fix(TL2CHICoupledL2): fix txrsp and txdat arbiter to RoundRobin (#415) The issue is that the txdat channel's arbiter, when handling a large number of requests, from 4 slices, is unable to respond slice#3 in a timely manner due to the limitations of the fixed-priority scheduling algorithm, considering slice#3 always has the lowest priority, which leads to the commit timeout.
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Squashed commit of the following: commit 8795306 Author: Yanqin Li <[email protected]> Date: Thu Oct 23 13:04:48 2025 +0800 refactor(pf): more concise TopDownMonitor (OpenXiangShan#435) * feat(prefetch): add l2 prefetch of berti * refactor(pf): more concise TopDownMonitor * fix(topdown): prefetch sent/useful summaried by dirResult not prefetchVec if the dirResults from diffrent bank have same prefetch soruce, the previous summary method by prefetchVec will omit the count. * submodule(utility): bump for new buskey commit c4550b1 Author: Yanqin Li <[email protected]> Date: Thu Oct 16 22:48:02 2025 +0800 feat(pf): add csr control of delay latency for l2 prefetch train (OpenXiangShan#434) commit 72416c4 Author: Yanqin Li <[email protected]> Date: Thu Oct 16 22:47:46 2025 +0800 feat(topdown): add the srouce output of late prefetch (OpenXiangShan#411) commit b754686 Author: Ma-YX <[email protected]> Date: Sun Sep 28 17:43:16 2025 +0800 Area(DataStorage): change Data SRAM's split to 4 (OpenXiangShan#432) Given the new physical-design backend requirements, changing the L2 Data SRAM specification to split = 4 is more favorable for both timing and area. commit abf2f74 Author: Tang Haojin <[email protected]> Date: Thu Sep 18 17:14:51 2025 +0800 build: bump chisel 7 and keep compatible with 6.7.0 (OpenXiangShan#431) commit 8c7dab9 Author: zhaohong1988 <[email protected]> Date: Fri Sep 5 16:41:03 2025 +0800 feat(MMIOBridge): exclude clint range inner xstilewrap to map the new clint ip (OpenXiangShan#429) commit 4a150c0 Author: Ding Haonan <[email protected]> Date: Mon Sep 1 13:14:22 2025 +0800 chore(TestTop): embedded CLog.B recording for CHI TestTop (OpenXiangShan#410) * submodule(utility): bump utility commit 5a610b4 Author: zhanglinjuan <[email protected]> Date: Wed Jul 16 11:30:49 2025 +0800 fix(MSHR): fix X-state propagation from RefillBuf (OpenXiangShan#426) For an MSHR entry handling AcquirePerm, the data in the corresponding RefillBuf is invalid. When the MSHR entry performs a replacement, it needs to write data in RefillBuf into DS, and the write enable signal `dsWen` of replacement request is always driven HIGH. This results in writing X-state data into DS. Although this theoretically does not cause bugs, it will trigger assertion in MCP2 check. commit d5f5c41 Author: Ding Haonan <[email protected]> Date: Fri Jul 11 18:42:24 2025 +0800 fix(Common, MSHR, MMIOBridge): reserve max QoS for real-time devices (OpenXiangShan#423) * Take ```MAX_QOS - 1``` for all CPU requests. commit 94f5f61 Author: yulightenyu <[email protected]> Date: Fri Jul 4 13:50:32 2025 +0800 fix(LinkLayer): fix exitcoDone signal right after reset (OpenXiangShan#424) * fix(Linklayer): fix exitcoDone singal right after reset This fix try to fix the false active of 'exitcoDone' the cycle after reset release. So as to resolve the CHI protocal 13.7.2: TXSACTIVE must be asserted when SYSCOREQ is high. * use && for single bit logic commit 5ab646e Author: yulightenyu <[email protected]> Date: Tue Jun 24 13:01:00 2025 +0800 fix(LinkLayer): fix linkactive time when power down (OpenXiangShan#422) when RN want to exit coherency (syscoreq=0), linkactive should NOT be deasserted before syscoack=0 indicating there is pending snoop on the way, so tx linkactive should keep active until syscozck==0 commit 70fe66f Author: yulightenyu <[email protected]> Date: Tue Jun 24 13:00:37 2025 +0800 fix(Linklayer): fix txsactive asserted before syscoreq after reset (OpenXiangShan#420) commit d0f0bd6 Author: Ding Haonan <[email protected]> Date: Tue Jun 17 13:52:31 2025 +0800 fix(MSHR): EWA always asserts on cacheable (revert OpenXiangShan#417) (OpenXiangShan#419) commit 9c1d363 Author: Ding Haonan <[email protected]> Date: Fri Jun 13 01:57:03 2025 +0800 fix(RequesterArb, MSHR): cancel replace task on read NDERR (OpenXiangShan#418) * fix(RequesterArb, MSHR): cancel replace task on read NDERR Co-authored-by: Ma-YX <[email protected]> commit 5a158eb Author: Ding Haonan <[email protected]> Date: Wed Jun 11 17:38:35 2025 +0800 fix(MSHR): deassert EWA for CMO transactions (OpenXiangShan#417) * To meet ISA specification, CMO instructions should only be returned after the consequence was visible to all **non-coherent** agents, which might be out of the CHI domain (e.g. DMAs on crossbars near to memory controller). commit 800bb00 Author: yulightenyu <[email protected]> Date: Sun Jun 1 17:10:16 2025 +0800 fix(TL2CHICoupledL2): fix txrsp and txdat arbiter to RoundRobin (OpenXiangShan#415) The issue is that the txdat channel's arbiter, when handling a large number of requests, from 4 slices, is unable to respond slice#3 in a timely manner due to the limitations of the fixed-priority scheduling algorithm, considering slice#3 always has the lowest priority, which leads to the commit timeout.
Ivyfeather
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Oct 30, 2025
Squashed commit of the following: commit 8795306 Author: Yanqin Li <[email protected]> Date: Thu Oct 23 13:04:48 2025 +0800 refactor(pf): more concise TopDownMonitor (OpenXiangShan#435) * feat(prefetch): add l2 prefetch of berti * refactor(pf): more concise TopDownMonitor * fix(topdown): prefetch sent/useful summaried by dirResult not prefetchVec if the dirResults from diffrent bank have same prefetch soruce, the previous summary method by prefetchVec will omit the count. * submodule(utility): bump for new buskey commit c4550b1 Author: Yanqin Li <[email protected]> Date: Thu Oct 16 22:48:02 2025 +0800 feat(pf): add csr control of delay latency for l2 prefetch train (OpenXiangShan#434) commit 72416c4 Author: Yanqin Li <[email protected]> Date: Thu Oct 16 22:47:46 2025 +0800 feat(topdown): add the srouce output of late prefetch (OpenXiangShan#411) commit b754686 Author: Ma-YX <[email protected]> Date: Sun Sep 28 17:43:16 2025 +0800 Area(DataStorage): change Data SRAM's split to 4 (OpenXiangShan#432) Given the new physical-design backend requirements, changing the L2 Data SRAM specification to split = 4 is more favorable for both timing and area. commit abf2f74 Author: Tang Haojin <[email protected]> Date: Thu Sep 18 17:14:51 2025 +0800 build: bump chisel 7 and keep compatible with 6.7.0 (OpenXiangShan#431) commit 8c7dab9 Author: zhaohong1988 <[email protected]> Date: Fri Sep 5 16:41:03 2025 +0800 feat(MMIOBridge): exclude clint range inner xstilewrap to map the new clint ip (OpenXiangShan#429) commit 4a150c0 Author: Ding Haonan <[email protected]> Date: Mon Sep 1 13:14:22 2025 +0800 chore(TestTop): embedded CLog.B recording for CHI TestTop (OpenXiangShan#410) * submodule(utility): bump utility commit 5a610b4 Author: zhanglinjuan <[email protected]> Date: Wed Jul 16 11:30:49 2025 +0800 fix(MSHR): fix X-state propagation from RefillBuf (OpenXiangShan#426) For an MSHR entry handling AcquirePerm, the data in the corresponding RefillBuf is invalid. When the MSHR entry performs a replacement, it needs to write data in RefillBuf into DS, and the write enable signal `dsWen` of replacement request is always driven HIGH. This results in writing X-state data into DS. Although this theoretically does not cause bugs, it will trigger assertion in MCP2 check. commit d5f5c41 Author: Ding Haonan <[email protected]> Date: Fri Jul 11 18:42:24 2025 +0800 fix(Common, MSHR, MMIOBridge): reserve max QoS for real-time devices (OpenXiangShan#423) * Take ```MAX_QOS - 1``` for all CPU requests. commit 94f5f61 Author: yulightenyu <[email protected]> Date: Fri Jul 4 13:50:32 2025 +0800 fix(LinkLayer): fix exitcoDone signal right after reset (OpenXiangShan#424) * fix(Linklayer): fix exitcoDone singal right after reset This fix try to fix the false active of 'exitcoDone' the cycle after reset release. So as to resolve the CHI protocal 13.7.2: TXSACTIVE must be asserted when SYSCOREQ is high. * use && for single bit logic commit 5ab646e Author: yulightenyu <[email protected]> Date: Tue Jun 24 13:01:00 2025 +0800 fix(LinkLayer): fix linkactive time when power down (OpenXiangShan#422) when RN want to exit coherency (syscoreq=0), linkactive should NOT be deasserted before syscoack=0 indicating there is pending snoop on the way, so tx linkactive should keep active until syscozck==0 commit 70fe66f Author: yulightenyu <[email protected]> Date: Tue Jun 24 13:00:37 2025 +0800 fix(Linklayer): fix txsactive asserted before syscoreq after reset (OpenXiangShan#420) commit d0f0bd6 Author: Ding Haonan <[email protected]> Date: Tue Jun 17 13:52:31 2025 +0800 fix(MSHR): EWA always asserts on cacheable (revert OpenXiangShan#417) (OpenXiangShan#419) commit 9c1d363 Author: Ding Haonan <[email protected]> Date: Fri Jun 13 01:57:03 2025 +0800 fix(RequesterArb, MSHR): cancel replace task on read NDERR (OpenXiangShan#418) * fix(RequesterArb, MSHR): cancel replace task on read NDERR Co-authored-by: Ma-YX <[email protected]> commit 5a158eb Author: Ding Haonan <[email protected]> Date: Wed Jun 11 17:38:35 2025 +0800 fix(MSHR): deassert EWA for CMO transactions (OpenXiangShan#417) * To meet ISA specification, CMO instructions should only be returned after the consequence was visible to all **non-coherent** agents, which might be out of the CHI domain (e.g. DMAs on crossbars near to memory controller). commit 800bb00 Author: yulightenyu <[email protected]> Date: Sun Jun 1 17:10:16 2025 +0800 fix(TL2CHICoupledL2): fix txrsp and txdat arbiter to RoundRobin (OpenXiangShan#415) The issue is that the txdat channel's arbiter, when handling a large number of requests, from 4 slices, is unable to respond slice#3 in a timely manner due to the limitations of the fixed-priority scheduling algorithm, considering slice#3 always has the lowest priority, which leads to the commit timeout.
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