fix(Hint): fix inaccurate l2hint in both single-slice and multi-slice contexts#465
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Frankslu wants to merge 11 commits intoOpenXiangShan:masterfrom
Open
fix(Hint): fix inaccurate l2hint in both single-slice and multi-slice contexts#465Frankslu wants to merge 11 commits intoOpenXiangShan:masterfrom
Frankslu wants to merge 11 commits intoOpenXiangShan:masterfrom
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Frankslu
requested review from
Ivyfeather,
Kumonda221-CrO3 and
linjuanZ
as code owners
linjuanZ
requested changes
Jan 14, 2026
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| val latch_grant_s4 = true | ||
| val pendingD_s4 = if (latch_grant_s4) { | ||
| task_s4.bits.fromA && !task_s4.bits.mshrTask && !need_write_releaseBuf_s4 && ( | ||
| task_s4.bits.opcode === GrantData || task_s4.bits.opcode === AccessAckData || task_s4.bits.opcode === Grant | ||
| ) | ||
| } else { | ||
| task_s4.bits.fromA && !task_s4.bits.mshrTask && ( | ||
| task_s4.bits.opcode === GrantData || task_s4.bits.opcode === AccessAckData | ||
| ) | ||
| } |
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There's no need to distinguish between the two cases if latch_grant_s4 is a constant value.
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| val allCanFire = ( | ||
| RegNextN(!hintChosenVec.map(_.valid).reduce(_ || _), sliceAhead) && | ||
| RegNextN(!hintChosenVec.map(h => h.valid && h.bits.hasData).reduce(_ || _), sliceAhead + 1)) || | ||
| Cat(releaseSourceD).orR |
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Suggested change
| val allCanFire = ( | |
| RegNextN(!hintChosenVec.map(_.valid).reduce(_ || _), sliceAhead) && | |
| RegNextN(!hintChosenVec.map(h => h.valid && h.bits.hasData).reduce(_ || _), sliceAhead + 1)) || | |
| Cat(releaseSourceD).orR | |
| val allCanFire = ( | |
| RegNextN(!hintChosenVec.map(_.valid).reduce(_ || _), sliceAhead) && | |
| RegNextN(!hintChosenVec.map(h => h.valid && h.bits.hasData).reduce(_ || _), sliceAhead + 1) | |
| ) || Cat(releaseSourceD).orR |
| // so we relax the restriction on grant selection. | ||
| val sliceCanFire = RegNextN(hintFire && i.U === hintChosen, sliceAhead) || | ||
| RegNextN(hintFire && i.U === hintChosen, sliceAhead + 1) | ||
| // val chosen = hintChosenVec.map(h => h.valid && h.bits.sliceId === i.U).reduce(_ || _) |
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| // val cancelable = Bool() | ||
| // cancelIdx = UInt(2.W) |
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| chn_AccessAckData_s3 -> AccessAckData | ||
| ) | ||
| ) | ||
| // enqBits_s3.cancelable := false.B |
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| // Don't remove this which can test retry | ||
| // val enable_force_retry = true | ||
| // val occWayMask_s2 = if(enable_force_retry) { | ||
| // val forceRetry = Counter(refillReqValid_s2, 4) | ||
| // Mux(forceRetry._1 === 0.U, | ||
| // ~0.U(ways.W), RegEnable(occWayMask_s1, io.read.fire && io.read.bits.refill)) | ||
| // } else { | ||
| // RegEnable(occWayMask_s1, io.read.fire && io.read.bits.refill) | ||
| // } | ||
|
|
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| val reqValid_s3 = RegNext(reqValid_s2, false.B) | ||
| val req_s2 = RegEnable(io.read.bits, 0.U.asTypeOf(io.read.bits), io.read.fire) | ||
| val req_s1 = io.read.bits | ||
| val req_s2 = RegEnable(req_s1, 0.U.asTypeOf(req_s1), io.read.fire) |
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Please confirm if req_s2 does not contain control signals. If so, do not initialize it.
| import utility.mbist.MbistPipeline | ||
| import coupledL2.utils._ | ||
| import utility.{ParallelPriorityMux, RegNextN, XSPerfAccumulate, Code} | ||
| import utility.{ParallelPriorityMux, RegNextN, XSPerfAccumulate, XSPerfHistogram, Code} |
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|
This pr should be merged into v3 branch after v3 branch is checked out. |
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This fix resolves the inaccurate L2 hint through two changes: