Upd modelsim simulation

Author: RDSik

.gitignore

@@ -7,7 +7,6 @@ sim/cocotb/*
 !si5340_config_loader_tb.py
 !wave.do
 sim/modelsim/*
-!Manifest.py
 !wave.do
 syn/*
 !Manifest.py

README.md

@@ -56,11 +56,11 @@ py -m pytest test.py
 deactivate
 ```
 
-### Using hdlmake:
+### Using macrofile:
 ```bash
 cd .\sim\modelsim\
-py -m hdlmake
-make
+vsim
+do wave.do
 ```
 
 ### Using Verilator:

sim/modelsim/Manifest.py

@@ -1,6 +1,23 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
+vlib work
+vmap work
 
+vlog ../../src/tb/si5340_config_loader_tb.sv
+vlog ../../src/tb/si5340_config_loader_if.sv
+vlog ../../src/tb/environment.sv
+vlog ../../src/i2c_master_bit_ctrl.v
+vlog ../../src/i2c_master_byte_ctrl.v
+vlog ../../src/i2c_master_defines.v
+vlog ../../src/timescale.v
+vlog ../../src/si5340_config_loader.sv
+vlog ../../src/i2c_ctrl_if.sv
+vlog ../../src/cfg_pkg.svh
+
+vsim -voptargs="+acc" si5340_config_loader_tb
+add log -r /*
+
+###############################
+# Add signals to time diagram #
+###############################
 add wave -expand -color #ff9911 -radix hex -group TOP \
 /si5340_config_loader_tb/dut/clk_i        \
 /si5340_config_loader_tb/dut/arstn_i      \

sim/modelsim/wave.do

@@ -14,34 +14,31 @@ class environment;
         this.dut_if = dut_if;
     endfunction
 
-    task init();
-        begin
-            dut_if.clk_i = 0;
-            reset();
-            read();
-            write();
-        end
-    endtask
-    
-    task reset();
+    task rst_gen();
         begin
             dut_if.arstn_i = 0;
-            $display("-----------------------------------------");
-            $display("Reset at %g ns.", $time);
-            $display("-----------------------------------------\n");
             #CLK_PER;
             dut_if.arstn_i = 1;
         end
     endtask
 
-    task write();
+    task run();
+        begin        
+            dut_if.clk_i = 0;
+            rst_gen();
+            rd_gen();
+            wr_gen();
+        end
+    endtask
+
+    task wr_gen();
         begin
             repeat(NUMBER) begin
                 dut_if.write_i = 1;
                 dut_if.load_i = 1;
                 $display("Load and Write at %g ns.", $time);
                 $display("-----------------------------------------");
-                #(CLK_PER*2);
+                @(posedge dut_if.clk_i);
                 dut_if.write_i = 0;
                 dut_if.load_i = 0;
                 #(CLK_PER*256);
@@ -52,14 +49,14 @@ class environment;
         end
     endtask
 
-    task read();
+    task rd_gen();
         begin
             repeat(NUMBER) begin
                 dut_if.write_i = 0;
                 dut_if.load_i = 1;
                 $display("Load and Read at %g ns.", $time);
                 $display("-----------------------------------------");
-                #(CLK_PER*2);
+                @(posedge dut_if.clk_i);
                 dut_if.write_i = 0;
                 dut_if.load_i = 0;
                 #(CLK_PER*256);

src/tb/environment.sv

@@ -30,7 +30,7 @@ module si5340_config_loader_tb();
     initial begin
         fork 
             env = new(dut_if);
-            env.init();
+            env.run();        
         join
         $finish;
     end