Upd sim for verilator

Author: RDSik

src/Makefile

@@ -18,7 +18,7 @@ SRC_FILES := $(shell find $(SRC_DIR) -name '*.vh')  \
 all: build execute simulate
 
 build:
-	$(VERILATOR) --trace --binary $(SRC_FILES) -I$(SRC_DIR) -I$(TB_DIR) --top $(TOP_NAME)_tb
+	$(VERILATOR) --binary $(SRC_FILES) --trace --trace-params --trace-structs -I$(SRC_DIR) -I$(TB_DIR) --top $(TOP_NAME)_tb
 
 execute:
 	./obj_dir/V$(TOP_NAME)_tb

src/i2c_master_bit_ctrl.v

@@ -256,6 +256,7 @@ module i2c_master_bit_ctrl (
       else if (rst || !ena ) filter_cnt <= 14'h0;
       // verilator lint_off WIDTHTRUNC
       else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
+      // verilator lint_on WIDTHTRUNC
       else                   filter_cnt <= filter_cnt -1;
 
 

src/i2c_master_byte_ctrl.v

@@ -341,5 +341,6 @@ module i2c_master_byte_ctrl (
 	            end
 
 	      endcase
+		  // verilator lint_on CASEINCOMPLETE
 	  end
 endmodule

src/tb/si5340_config_loader_tb.sv

@@ -2,6 +2,7 @@
 
 /* verilator lint_off MODDUP */
 module si5340_config_loader_tb();
+/* verilator lint_on MODDUP */
 
     si5340_config_loader_if dut_if();
     environment env;