Merge branch 'master' of https://github.com/RDSik/si5340-config-loader

Author: RDSik

.gitignore

@@ -1,4 +1,4 @@
-sim/verilator/cocotb/*
+sim/verilator/*
 !si5340_config_loader_tb.py
 !si5340_config_loader.sv
 !test.py

Dockerfile

@@ -27,4 +27,5 @@ RUN git clone https://github.com/verilator/verilator && \
 
 COPY . .
 
-RUN make
+RUN cd src && \
+    make

LICENSE.txt

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2024 Dmitry Ryabikov
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

config.mem

@@ -6,7 +6,7 @@
 from cocotb.runner import get_runner
 
 def test_runner():
-    src = Path("../../../src")
+    src = Path("../../src")
 
     hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog")
     sim = os.getenv("SIM", "verilator")