Zen3

Architecture specific notes for AMD K19 (Zen3)

Performance groups

AMD Zen3 Performance groups

Events

The input file for the events on AMD Zen3 can be found here.

Counters

• HWthread-local counters
  • Fixed-purpose counters
  • General-purpose counters
• Core-local counters
  • Core energy counters
• Cache-wide counters
  • L3 general-purpose counters
• Socket-wide counters
  • Socket energy counters
  • Data fabric counters

HWthread-local counters

Fixed-purpose counters

The AMD® Zen3 microarchitecture provides three fixed-purpose counters for retired instructions, actual CPU core clock (MPerf: This register increments in proportion to the actual number of core clocks cycles while the core is in C0) and maximum CPU core clock (APerf: Incremented by hardware at the P0 frequency while the core is in C0).

Counters

Counter name	Event name
FIXC0	N/A
FIXC1	N/A
FIXC2	N/A

General-purpose counters

The AMD® Zen3 microarchitecture provides 6 general-purpose counters consisting of a config and a counter register.

Counters

Counter name	Event name
PMC0	*
PMC1	*
PMC2	*
PMC3	*
PMC4	*
PMC5	*

Available Options

Option	Argument	Operation	Comment
edgedetect	N	Set bit 18 in config register
invert	N	Set bit 23 in config register
kernel	N	Set bit 17 in config register
threshold	8 bit hex value	Set bits 24-31 in config register	The value for threshold can range between 0x0 and 0x7F

Core-local counters

Core energy counters

The AMD® Zen3 microarchitecture provides 2 energy counters (RAPL) for CPU core and package energy.

Counters

Counter name	Event name
PWR0	RAPL_CORE_ENERGY

Cache-wide counters

L3 general-purpose counters

The AMD® Zen3 microarchitecture provides 6 general-purpose counters for measuring L3 cache events. They consist of a config and a counter register. The counters are related to a shared L3 cache, hence you get only one value per L3 cache.

Counters

Counter name	Event name
CPMC0	*
CPMC1	*
CPMC2	*
CPMC3	*
CPMC4	*
CPMC5	*

Available Options

Option	Argument	Operation	Comment
tid	8 bit hex value	Set bits 56 to 63 in config register	Selects whether the accesses of an attached thread should be counted. Default all threads: 0xFF
cid	3 bit hex value	Set bits 42 to 45 in config register	Selects which core should be counted. If not specified, the all-cores flag (bit 47) is set
slice	4 bit hex value	Set bits 48 to 51 in config register	Selects which L3 slice should be counted. If not specified, the all-slices flag (bit 46) is set

Socket-wide counters

Socket energy counters

The AMD® Zen3 microarchitecture provides 2 energy counters (RAPL) for CPU core and package energy.

Counters

Counter name	Event name
PWR1	RAPL_PKG_ENERGY

Data fabric counters

The AMD® Zen3 microarchitecture provides 4 data fabric counters (DF) once per socket.

Counters

Counter name	Event name
DFC0	*
DFC1	*
DFC2	*
DFC3	*