Skip to content

This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.

Notifications You must be signed in to change notification settings

RichardPar/SDRAM_Controller_Verilog

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

10 Commits
 
 
 
 
 
 
 
 
 
 

Repository files navigation

SDRAM_Controller_Verilog

This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz. My development board is from QMtech https://qmtechchina.aliexpress.com/store/4486047

Development board

Decode Logic

Address BANK/RAS/CAS are as follows Decode Logic

About

This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.

Topics

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published