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@Unicamp-Odhin

Open Design and Hardware Initiative

Unicamp Open Design and Hardware Initiative
README.md

UNICAMP Odhin

Open Design and Hardware Initiative

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  1. I2S_Microphone I2S_Microphone Public

    I2S Microphone peripheral written in SystemVerilog HDL

    Tcl 4

  2. Rofofo Rofofo Public

    Audio Processing and AI Acceleration with FPGA

    Verilog 4

  3. MFCC_Core MFCC_Core Public

    MFCC Core written in SystemVerilog

    Verilog 3

  4. GPIO_Peripheral GPIO_Peripheral Public

    GPIO Peripheral written in SystemVerilog HDL

    SystemVerilog 1

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