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Merge remote-tracking branch 'github/master' into Vivado
Conflicts: README.md src/common/physical.vhdl
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‎.appveyor.yml

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version: 1.1.0-b{build}
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clone_folder: c:\projects\poc
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init:
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# Checking that DEP is enabled
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- ps: Write-Host "Initializing virtual machine ..."
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- ps: git --version
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- ps: $env:Path = $env:Path.Replace("Python27", "Python35-x64")
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install:
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- ps: Write-Host "Installing requirements..."
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- ps: python --version
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- ps: python -m pip install pip --upgrade
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- ps: python -m pip install -r .\requirements.txt
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- ps: python -m pip list --format=columns
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- ps: Write-Host "Configuring PoC..."
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- ps: cp .\tools\AppVeyor\config.private.ini .\py\
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- ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\
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- ps: .\poc.ps1
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build: off
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build_script:
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- ps: Write-Host "Testing query interface..."
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- ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory
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- ps: Write-Host "Testing information interface..."
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- ps: .\poc.ps1 list-testbench PoC.*
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- ps: .\poc.ps1 list-netlist PoC.*
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- ps: Write-Host "Testing simulators..."
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- ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate
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- ps: Write-Host "Testing synthesizers..."
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# - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4
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# - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa
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# - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705
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# - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705
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# - ps: Write-Host "Testing core generators..."
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# - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys

‎.gitignore

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__pycache__
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# ignore build directories
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docs/_build/
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/docs/_build/
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/docs/PyInfrastructure/*
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!/docs/PyInfrastructure/.gitempty
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!/docs/PyInfrastructure/.publish
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!/docs/PyInfrastructure/README.md
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!/docs/PyInfrastructure/index.rst
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# ignore files in netlist/
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/netlist/
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!.git*
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!.publish
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!README.md
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other/PrecisionRTL/

‎.gitmodules

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[submodule "docs/_themes/sphinx_rtd_theme"]
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path = docs/_themes/sphinx_rtd_theme
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url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git
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[submodule "lib/uvvm"]
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path = lib/uvvm
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url = https://github.com/VLSI-EDA/UVVM_All.git

‎.landscape.yml

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- sim
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- src
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# - tb
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- tcl
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- temp
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# - tools
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- ucf

‎.readthedocs.yml

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#formats:
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# - pdf
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requirements_file: tools/ReadTheDocs/requirements.txt
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python:
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version: 3

‎README.md

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[![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/Vivado/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/Vivado)
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[![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=Vivado)](https://travis-ci.org/VLSI-EDA/PoC/branches)
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[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/Vivado?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/Vivado)
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[![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest)
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[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=Vivado)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=Vivado)
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[![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC)
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![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)
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[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)
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A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
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- [OS-VVM][2132]
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Open Source VHDL Verification Methodology.
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- [VUnit][2133]
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- [UVVM][2133]
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Universal VHDL Verification Methodology.
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- [VUnit][2134]
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An unit testing framework for VHDL.
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All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the
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[`PoCRoot\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries.
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[2131]: https://github.com/potentialventures/cocotb
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[2132]: https://github.com/JimLewis/OSVVM
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[2133]: https://github.com/VUnit/vunit
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[2133]: https://github.com/UVVM/UVVM_All
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[2134]: https://github.com/VUnit/vunit
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[201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html
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[202]: http://poc-library.readthedocs.io/
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### 2.2 Download
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The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone`
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The PoC-Library can be downloaded as a [zip-file][221] (latest 'Vivado' branch), cloned with `git clone`
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or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See
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the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`.
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‎README.tpl

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[![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@})
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[![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches)
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[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/{@BRANCH@}?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/{@BRANCH@})
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[![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest)
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[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch={@BRANCH@})](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch={@BRANCH@})
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[![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC)
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![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)
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[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)
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[![Apache License 2.0](https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat)](LICENSE.md)
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This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** -
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Faculty of Computer Science, Technische Universität Dresden, Germany
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**http://vlsi-eda.inf.tu-dresden.de**
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## 2 Quick Start Guide
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This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in the
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[Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples.
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This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in
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the [Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples.
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### 2.1 Requirements and Dependencies
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A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
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- [OS-VVM][2132]
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Open Source VHDL Verification Methodology.
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- [VUnit][2133]
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- [UVVM][2133]
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Universal VHDL Verification Methodology.
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- [VUnit][2134]
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An unit testing framework for VHDL.
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[`PoCRoot\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries.
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[2133]: https://github.com/UVVM/UVVM_All
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[2134]: https://github.com/VUnit/vunit
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[201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html
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[202]: http://poc-library.readthedocs.io/
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### 2.2 Download
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The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone`
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The PoC-Library can be downloaded as a [zip-file][221] (latest '{@BRANCH@}' branch), cloned with `git clone`
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or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See
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the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`.
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‎docs/ChangeLog/2014/index.rst

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.. _CHANGE:2014:
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2014
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####
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.. contents:: Content of this page
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:local:
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.. toctree::
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v0.0.0 <v0.0.0>

‎docs/ChangeLog/2014/v0.0.0.rst

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.. _CHANGE:v0.0.0:
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New in v0.0.0 (16.12.2014)
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================================================================================================================================================================
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* Initial commit

‎docs/ChangeLog/2015/index.rst

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.. _CHANGE:2015:
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2015
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####
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.. contents:: Content of this page
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:local:
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.. only:: html
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.. toctree::
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v0.18.0 <v0.18.0>
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v0.17.0 <v0.17.0>
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v0.16.0 <v0.16.0>
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v0.15.0 <v0.15.0>
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v0.14.0 <v0.14.0>
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v0.13.0 <v0.13.0>
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v0.12.0 <v0.12.0>
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v0.11.0 <v0.11.0>
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v0.10.0 <v0.10.0>
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v0.9.0 <v0.9.0>
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v0.8.0 <v0.8.0>
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v0.7.0 <v0.7.0>
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v0.6.0 <v0.6.0>
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v0.5.0 <v0.5.0>
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v0.4.0 <v0.4.0>
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v0.3.0 <v0.3.0>
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v0.2.0 <v0.2.0>
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v0.1.0 <v0.1.0>
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.. only:: latex
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.. toctree::
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v0.1.0 <v0.1.0>
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v0.2.0 <v0.2.0>
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v0.3.0 <v0.3.0>
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v0.4.0 <v0.4.0>
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v0.5.0 <v0.5.0>
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v0.6.0 <v0.6.0>
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v0.7.0 <v0.7.0>
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v0.8.0 <v0.8.0>
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v0.9.0 <v0.9.0>
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v0.10.0 <v0.10.0>
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v0.11.0 <v0.11.0>
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v0.12.0 <v0.12.0>
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v0.13.0 <v0.13.0>
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v0.14.0 <v0.14.0>
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v0.15.0 <v0.15.0>
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v0.16.0 <v0.16.0>
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v0.17.0 <v0.17.0>
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v0.18.0 <v0.18.0>

‎docs/ChangeLog/2015/v0.1.0.rst

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.. :CHANGE:v0.1.0:
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New in v0.1.0 (19.02.2015)
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================================================================================================================================================================
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* New packages:
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* board - common development board configurations
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* config - extract configuration parameters from device names
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* utils - common utility functions
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* strings - a helper package for string handling
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* vectors - a helper package for std_logic_vector and std_logic_matrix
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* arith
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* fifo
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* New modules
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* arith_counter_gray
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* arith_counter_ring
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* arith_div
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* arith_prefix_and
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* arith_prefix_or
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* arith_prng
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* arith_scaler
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* arith_sqrt
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* PoC.fifo - FIFOs
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* fifo_cc_got
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* fifo_cc_got_tempgot
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* fifo_cc_got_tempput
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* fifo_ic_got
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* fifo_glue
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* fifo_shift
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* PoC.mem.ocram - On-Chip RAMs
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* ocram_sp
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* ocram_sdp
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* ocram_esdp
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* ocram_tdp
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* ocram_wb

‎docs/ChangeLog/2015/v0.10.0.rst

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.. :CHANGE:v0.10.0:
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New in v0.10.0 (23.07.2015)
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================================================================================================================================================================

‎docs/ChangeLog/2015/v0.11.0.rst

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New in v0.11.0 (07.08.2015)
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================================================================================================================================================================

‎docs/ChangeLog/2015/v0.12.0.rst

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================================================================================================================================================================

‎docs/ChangeLog/2015/v0.13.0.rst

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================================================================================================================================================================

‎docs/ChangeLog/2015/v0.14.0.rst

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New in v0.14.0 (28.09.2015)
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‎docs/ChangeLog/2015/v0.15.0.rst

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‎docs/ChangeLog/2015/v0.16.0.rst

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‎docs/ChangeLog/2015/v0.17.0.rst

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‎docs/ChangeLog/2015/v0.18.0.rst

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================================================================================================================================================================

‎docs/ChangeLog/2015/v0.2.0.rst

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================================================================================================================================================================
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* New packages:
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* stream
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* New modules:
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* bus_Arbiter
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* PoC.bus.stream - Modules for the PoC.Stream protocol
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* stream_Buffer
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* stream_Mirror
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* stream_Source
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* xil_SyncReset
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* xil_BSCAN
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* xil_Reconfigurator
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* xil_SystemMonitor_Virtex6
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* xil_SystemMonitor_Series7
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* Updated packages:
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* utils
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* arith

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