VLSI Design & Automation Group
UC Santa Cruz VLSI Design and Automation research lab
- 167 followers
- Santa Cruz, CA
- http://vlsida.github.io
- mrg+vlsida@ucsc.edu
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Repositories
Showing 10 of 34 repositories
- UCSC_ML_suite Public
VLSIDA/UCSC_ML_suite’s past year of commit activity - OpenROAD Public Forked from The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
VLSIDA/OpenROAD’s past year of commit activity - bsg_fakeram Public Forked from bespoke-silicon-group/bsg_fakeram
fakeram generator for use by researchers who do not have access to commercial ram generators
VLSIDA/bsg_fakeram’s past year of commit activity - chip-tutorials Public
VLSIDA/chip-tutorials’s past year of commit activity - OpenROAD-flow-scripts Public Forked from The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
VLSIDA/OpenROAD-flow-scripts’s past year of commit activity - sky130_fd_bd_sram Public
VLSIDA/sky130_fd_bd_sram’s past year of commit activity - openlane2 Public Forked from efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
VLSIDA/openlane2’s past year of commit activity - vlsida-openroad Public
VLSIDA/vlsida-openroad’s past year of commit activity -
VLSIDA/openram_testchip’s past year of commit activity
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