Assertion Error in SRAM Generation with Specific word_size and num_words Configurations

[riagus99]

Describe the bug
I attempted to generate an SRAM instance using the following command:

python $OPENRAM_HOME/../sram_compiler.py myconfig.py

While some configurations work perfectly, others fail to execute. I'm not sure if I'm using an unsupported configuration or if this could be a bug in OpenRAM.

Below, I've listed the configurations that work and those that do not.

Working configurations

• word_size = 8, num_words = 32
• word_size = 64, num_words = 2048

Not working configurations

• word_size = 32, num_words = 100
• word_size = 48, num_words = 96
• word_size = 96, num_words = 96

Version
commit b6a6f12

To Reproduce
As an example, here is the configuration that fails (word_size = 32, num_words = 100).

python version: Python 3.8.19

configuration file (myconfig.py)

num_rw_ports    = 1
num_r_ports     = 0
num_w_ports     = 0

# Number of bits per word
word_size = 32
# Number of words (some people call this 'depth')
num_words = 100

# The fabrication technology. This must match the PDK name in $OPENRAM_TECH.
tech_name = "freepdk45"

# Process corners, temperature and voltage to characterize
process_corners = ["TT"]
supply_voltages = [0.9]
temperatures = [40]
nominal_corner_only = True

route_supplies  = False
#check_lvsdrc = True

#output_path     = "SRAM_{0}x{1}_r1_w1".format(word_size, num_words)
#output_name     = "SRAM_{0}x{1}_r1_w1".format(word_size, num_words)
#instance_name   = "SRAM_{0}x{1}_r1_w1".format(word_size, num_words)
output_path     = "SRAM_{0}x{1}_rw{2}_r{3}_w{4}".format(word_size, num_words, num_rw_ports, num_r_ports, num_w_ports)
output_name     = "SRAM_{0}x{1}_rw{2}_r{3}_w{4}".format(word_size, num_words, num_rw_ports, num_r_ports, num_w_ports)
instance_name     = "SRAM_{0}x{1}_rw{2}_r{3}_w{4}".format(word_size, num_words, num_rw_ports, num_r_ports, num_w_ports)

Logs
Below is the output I received:

|==============================================================================|
|=========                      OpenRAM v1.2.48                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: [email protected]           =========|
|=========        Development help: [email protected]        =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 08/18/2024 07:42:04
Technology: freepdk45
Total size: 3200 bits
Word size: 32
Words: 100                                                                                                                                                                                                                                                                                                                                                           Banks: 1                                                                                                                                                                                                                                                                                                                                                             RW ports: 1                                                                                                                                                                                                                                                                                                                                                          R-only ports: 0                                                                                                                                                                                                                                                                                                                                                      W-only ports: 0                                                                                                                                                                                                                                                                                                                                                      Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).                                                                                                                                                                                                                                        DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).                                                                                                                                                                                                                                                                                                               Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).                                                                                                                                                                                                                                                                   Only generating nominal corner timing.                                                                                                                                                                                                                                                                                                                               Words per row: None                                                                                                                                                                                                                                                                                                                                                  Output files are:                                                                                                                                                                                                                                                                                                                                                    /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.lvs                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.sp
/root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.v                                                                                                                                                                                                                                                                                            /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.lib                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.py                                                                                                                                                                                                                                                                                           /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.html                                                                                                                                                                                                                                                                                         /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.log                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.lef                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.gds
** Submodules: 15.0 seconds
** Placement: 0.1 seconds
** Routing: 140.9 seconds
** Verification: 0.0 seconds
** SRAM creation: 155.9 seconds
SP: Writing to /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.sp
** Spice writing: 0.3 seconds
DELAY: Writing stimulus...                                                                                                                        ERROR: file simulation.py: line 606: Could not find bl net in timing paths.                                                                                                                                                                                                                                                                                          Traceback (most recent call last):                                                                                                                                                                                                                                                                                                                                     File "/root/verilog_works/OpenRAM/compiler/../sram_compiler.py", line 76, in <module>                                                                                                                                                                                                                                                                                  s.save()                                                                                                                                                                                                                                                                                                                                                           File "/root/verilog_works/OpenRAM/compiler/sram.py", line 130, in save                                                                                                                                                                                                                                                                                                 d.analysis_init(probe_address, probe_data)
  File "/root/verilog_works/OpenRAM/compiler/characterizer/delay.py", line 1288, in analysis_init                                                                                                                                                                                                                                                                        self.set_internal_spice_names()                                                                                                                                                                                                                                                                                                                                    File "/root/verilog_works/OpenRAM/compiler/characterizer/simulation.py", line 520, in set_internal_spice_names                                                                                                                                                                                                                                                         bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)                                                                                                                                                                                                                                                                                          File "/root/verilog_works/OpenRAM/compiler/characterizer/simulation.py", line 625, in get_bl_name                                                                                                                                                                                                                                                                      bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))                                                                                                                                                                                                                                                                                     File "/root/verilog_works/OpenRAM/compiler/characterizer/simulation.py", line 606, in get_alias_in_path
    debug.error("Could not find {} net in timing paths.".format(internal_net), 1)                                                                                                                                                                                                                                                                                      File "/root/verilog_works/OpenRAM/compiler/debug.py", line 48, in error                                                                                                                                                                                                                                                                                                assert return_value == 0                                                                                                                                                                                                                                                                                                                                         AssertionError                                                                                                                                                                                                                                                                                                                                                       

Additional context
I have reviewed the documentation but could not find any constraints related to the configuration that could explain this issue. If there are specific constraints that I should be aware of, could you please provide some guidance?

[mguthaus]

Yes, this is a duplicate of #228

[srd8668]

is there any previously working git version or tag which i can switch to generate sram macros reliably for sky130 PDK

[srd8668]

if we make analytical_delay=False we will get the below issue during characterization
ERROR: file stimuli.py: line 421: Spice simulation error: /bin/bash -c 'source /home/diat_Master/deepak/OpenRAM/miniconda/bin/activate && /home/diat_Master/deepak/OpenRAM/miniconda/bin/mpirun -np 28 /home/diat_Master/deepak/OpenRAM/miniconda/bin/Xyce -r /tmp/openram_diat_Master_37659_temp/timing.raw -o /tmp/openram_diat_Master_37659_temp/timing.lis /tmp/openram_diat_Master_37659_temp/delay_stim.sp && conda deactivate'
Traceback (most recent call last):
File "/home/diat_Master/deepak/OpenRAM/compiler/../sram_compiler.py", line 76, in
s.save()
File "/home/diat_Master/deepak/OpenRAM/compiler/sram.py", line 191, in save
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/lib.py", line 46, in init
self.characterize_corners()
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/lib.py", line 164, in characterize_corners
self.characterize()
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/lib.py", line 176, in characterize
self.compute_delay()
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/lib.py", line 656, in compute_delay
char_results = self.d.analyze(probe_address, probe_data, self.load_slews)
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/delay.py", line 1309, in analyze
feasible_delays = self.find_feasible_period()
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/delay.py", line 786, in find_feasible_period
feasible_delays[self.read_ports[0]] = self.find_feasible_period_one_port(self.read_ports[0])
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/delay.py", line 752, in find_feasible_period_one_port
(success, results)=self.run_delay_simulation()
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/delay.py", line 817, in run_delay_simulation
self.stim.run_sim(self.delay_stim_sp)
File "/home/diat_Master/deepak/OpenRAM/compiler/characterizer/stimuli.py", line 421, in run_sim
debug.error("Spice simulation error: " + cmd, -1)
File "/home/diat_Master/deepak/OpenRAM/compiler/debug.py", line 48, in error
assert return_value == 0
AssertionError

and if we make dont touch use this analytical delay line and make inline_lvsdrc=False then its generating the files successfully. But iam going to fabricate it it fails due to inline_lvsdrc then i dont think the output generated without it is reliable.

[mguthaus]

inline_lvsdrc runs LVS and DRC at every hierarchical level instead of only at the end. You shouldn't turn this on for sky130 since the bitcells cannot pass on their own. They have devices that are split between two bitcells so they won't pass alone.

This feature is just meant to help debugging when there is a failure to help isolate an error. OpenRAM will still run LVS and DRC at the top level as long as check_lvsdrc is enabled.

[srd8668]

Thanks for the reply i will try this and let you know if i face any other problem.

[srd8668]

Hi,
I was able to generate SRAM with the below config, my question here is currently i made analytical_delay=True and generated, can i use the generated gds and lef files fabrication or should i generate it by making analytical_delay=False and use it for my Chip. Iam intending to have a dual port sram for parallel read and write operations with operational frequency of 200MHZ.

Data word size

word_size = 32

Number of words in the memory

num_words = 256

need to check what the below does

write_size = 8

num_rw_ports = 2

Technology to use in $OPENRAM_TECH

tech_name = "sky130"

Process corners to characterize

process_corners = [ "TT" ]

Voltage corners to characterize

supply_voltages = [ 1.8 ]

Temperature corners to characterize

temperatures = [ 100 ]

Output directory for the results

output_path = "temp_32_1024_master_last_stable_2rw"

Output file base name

output_name = "sram_32x1024"
check_lvsdrc=True
output_datasheet_info = True
netlist_only = False

Disable analytical models for full characterization (WARNING: slow!)

analytical_delay = True

To force this to use magic and netgen for DRC/LVS/PEX

Could be calibre for FreePDK45

drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"

[mguthaus]

I would suggest that you get simulation working to verify a 200MHz operation.

[srd8668]

Simulation in the sense of SPICE simulation, or are you referring to RTL simulation with the Verilog model which got generated to verify the 200 MHz operation?

[mguthaus]

Spice.

[srd8668]

Sure, thank you! I have one last question: Currently, I’ve generated the SRAM with analytical_delay=True. Can I use this version directly for fabrication, or do I need to regenerate it with analytical_delay=False and use the resulting GDS/LEF in my design?

[mguthaus]

The characterization model used won't change the layout and implementation. So both will result in the same design layout, but the .lib file with delay and power will be different.

[srd8668]

Thanks for the information.