This repository contains two variants of the TIDC design:
- Standard Variant: Original parameterized design
- Verilator Variant: De-parameterized version optimized for Verilator simulation
TIDC/
├── variants/
│ ├── standard/ # Original parameterized version
│ │ ├── rtl/ # RTL source files
│ │ ├── tb/ # Testbenches
│ │ └── Makefile # Variant-specific Makefile
│ └── verilator/ # De-parameterized verilator version
│ ├── rtl/ # RTL source files
│ ├── tb/ # Testbenches and C++ testbench
│ └── Makefile # Variant-specific Makefile
├── common/ # Shared utilities (if any)
├── docs/ # Documentation
├── Makefile # Top-level Makefile for variant selection
├── README.md
└── .gitignore
The top-level Makefile supports both variants. Use the VARIANT parameter to select which version to build:
# Build and run verilator variant (default)
make
# Build and run standard variant
make VARIANT=standard
# Build and run verilator variant explicitly
make VARIANT=verilator
# View waveforms for verilator variant
make VARIANT=verilator waves
# Run lint check on standard variant
make VARIANT=standard lint
# Clean all variants
make clean-all
# Test both variants
make test-all
# List available variants
make list-variants- Location:
variants/standard/ - Features: Full parameterized design
- Simulation: Standard Verilog simulator compatible
- Build:
make VARIANT=standard sim
- Location:
variants/verilator/ - Features: De-parameterized for Verilator compatibility
- Simulation: Verilator with C++ testbench
- Build:
make VARIANT=verilator simor justmake
Switching between variants:
# Work on verilator variant
cd variants/verilator
make sim
# Work on standard variant
cd variants/standard
make simTesting both variants:
# Test all variants from root
make test-allWhen contributing:
- Determine which variant(s) your changes affect
- Make changes in the appropriate
variants/directory - Test using the variant-specific workflow
- Consider impact on other variants
- Update documentation if needed