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1 | 1 | /* |
2 | 2 | * Copyright (c) 2022, Xilinx, Inc. |
3 | | - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. |
| 3 | + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. |
4 | 4 | * All rights reserved. |
5 | 5 | * |
6 | 6 | * Author: Eddie Hung, Xilinx Research Labs. |
|
24 | 24 | package com.xilinx.rapidwright.design; |
25 | 25 |
|
26 | 26 |
|
| 27 | +import com.xilinx.rapidwright.device.BELPin; |
27 | 28 | import com.xilinx.rapidwright.device.Device; |
28 | 29 | import com.xilinx.rapidwright.support.RapidWrightDCP; |
29 | 30 | import com.xilinx.rapidwright.util.FileTools; |
|
32 | 33 | import org.junit.jupiter.api.Test; |
33 | 34 | import org.junit.jupiter.params.ParameterizedTest; |
34 | 35 | import org.junit.jupiter.params.provider.CsvSource; |
| 36 | +import org.junit.jupiter.params.provider.ValueSource; |
35 | 37 |
|
| 38 | +import java.util.Arrays; |
36 | 39 | import java.util.List; |
37 | 40 |
|
38 | 41 | public class TestCell { |
@@ -110,4 +113,38 @@ public void testFFRoutethruCell() { |
110 | 113 | Assertions.assertEquals(0, VivadoTools.reportRouteStatus(d).netsWithRoutingErrors); |
111 | 114 | } |
112 | 115 | } |
| 116 | + |
| 117 | + @ParameterizedTest |
| 118 | + @ValueSource(booleans = {true, false}) |
| 119 | + void testGetSitePinFromLogicalPin(boolean createAX) { |
| 120 | + Design design = new Design("top", Device.PYNQ_Z1); |
| 121 | + SiteInst si = design.createSiteInst("SLICE_X1Y0"); |
| 122 | + Net net = design.createNet("net"); |
| 123 | + SitePinInst A3 = net.createPin("A3", si); |
| 124 | + SitePinInst AX = (createAX) ? net.createPin("AX", si) : null; |
| 125 | + |
| 126 | + Cell ff = design.createAndPlaceCell("ff", Unisim.FDRE, "SLICE_X1Y0/AFF"); |
| 127 | + |
| 128 | + BELPin ffD = ff.getBEL().getPin("D"); |
| 129 | + for (SitePinInst spi : Arrays.asList(AX, A3)) { |
| 130 | + if (spi == null) |
| 131 | + continue; |
| 132 | + |
| 133 | + Assertions.assertNull(DesignTools.getRoutedSitePin(ff, net, "D")); |
| 134 | + if (createAX) { |
| 135 | + // FIXME: Known broken -- see https://github.com/Xilinx/RapidWright/issues/473 |
| 136 | + Assertions.assertEquals("IN SLICE_X1Y0.AX", ff.getSitePinFromLogicalPin("D", null).toString()); |
| 137 | + } else { |
| 138 | + Assertions.assertNull(ff.getSitePinFromLogicalPin("D", null)); |
| 139 | + } |
| 140 | + |
| 141 | + BELPin bp = spi.getBELPin(); |
| 142 | + Assertions.assertTrue(si.routeIntraSiteNet(net, bp, ffD)); |
| 143 | + |
| 144 | + Assertions.assertEquals(bp.getName(), DesignTools.getRoutedSitePin(ff, net, "D")); |
| 145 | + Assertions.assertEquals(spi, ff.getSitePinFromLogicalPin("D", null)); |
| 146 | + |
| 147 | + Assertions.assertTrue(si.unrouteIntraSiteNet(bp, ffD)); |
| 148 | + } |
| 149 | + } |
113 | 150 | } |
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