Skip to content

Commit 831605c

Browse files
committed
Add TestCell.testGetSitePinFromLogicalPin() with known broken
Signed-off-by: Eddie Hung <[email protected]>
1 parent 425d89e commit 831605c

File tree

1 file changed

+38
-1
lines changed

1 file changed

+38
-1
lines changed

test/src/com/xilinx/rapidwright/design/TestCell.java

Lines changed: 38 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2022, Xilinx, Inc.
3-
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
3+
* Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
44
* All rights reserved.
55
*
66
* Author: Eddie Hung, Xilinx Research Labs.
@@ -24,6 +24,7 @@
2424
package com.xilinx.rapidwright.design;
2525

2626

27+
import com.xilinx.rapidwright.device.BELPin;
2728
import com.xilinx.rapidwright.device.Device;
2829
import com.xilinx.rapidwright.support.RapidWrightDCP;
2930
import com.xilinx.rapidwright.util.FileTools;
@@ -32,7 +33,9 @@
3233
import org.junit.jupiter.api.Test;
3334
import org.junit.jupiter.params.ParameterizedTest;
3435
import org.junit.jupiter.params.provider.CsvSource;
36+
import org.junit.jupiter.params.provider.ValueSource;
3537

38+
import java.util.Arrays;
3639
import java.util.List;
3740

3841
public class TestCell {
@@ -110,4 +113,38 @@ public void testFFRoutethruCell() {
110113
Assertions.assertEquals(0, VivadoTools.reportRouteStatus(d).netsWithRoutingErrors);
111114
}
112115
}
116+
117+
@ParameterizedTest
118+
@ValueSource(booleans = {true, false})
119+
void testGetSitePinFromLogicalPin(boolean createAX) {
120+
Design design = new Design("top", Device.PYNQ_Z1);
121+
SiteInst si = design.createSiteInst("SLICE_X1Y0");
122+
Net net = design.createNet("net");
123+
SitePinInst A3 = net.createPin("A3", si);
124+
SitePinInst AX = (createAX) ? net.createPin("AX", si) : null;
125+
126+
Cell ff = design.createAndPlaceCell("ff", Unisim.FDRE, "SLICE_X1Y0/AFF");
127+
128+
BELPin ffD = ff.getBEL().getPin("D");
129+
for (SitePinInst spi : Arrays.asList(AX, A3)) {
130+
if (spi == null)
131+
continue;
132+
133+
Assertions.assertNull(DesignTools.getRoutedSitePin(ff, net, "D"));
134+
if (createAX) {
135+
// FIXME: Known broken -- see https://github.com/Xilinx/RapidWright/issues/473
136+
Assertions.assertEquals("IN SLICE_X1Y0.AX", ff.getSitePinFromLogicalPin("D", null).toString());
137+
} else {
138+
Assertions.assertNull(ff.getSitePinFromLogicalPin("D", null));
139+
}
140+
141+
BELPin bp = spi.getBELPin();
142+
Assertions.assertTrue(si.routeIntraSiteNet(net, bp, ffD));
143+
144+
Assertions.assertEquals(bp.getName(), DesignTools.getRoutedSitePin(ff, net, "D"));
145+
Assertions.assertEquals(spi, ff.getSitePinFromLogicalPin("D", null));
146+
147+
Assertions.assertTrue(si.unrouteIntraSiteNet(bp, ffD));
148+
}
149+
}
113150
}

0 commit comments

Comments
 (0)