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Pull requests: Xilinx/RapidWright
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Add ability to constrain flop harness to specific side of PBlock
#1318
opened Nov 7, 2025 by
abutt-amd
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[VersalClockRouting] VDISTR tree storage map for Versal
#1311
opened Nov 4, 2025 by
clavin-xlnx
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Adds external library for netlists to compensate for black boxed cells
#1294
opened Oct 7, 2025 by
clavin-xlnx
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Fix DesignTools.getConnectionPips for sinks driven by lut constant generators
#1231
opened Jun 20, 2025 by
reillymck
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Array Builder Tool - Replicate Optimized Kernels in an Array
#1163
opened Apr 10, 2025 by
clavin-xlnx
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Draft
[EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()
#1148
opened Feb 14, 2025 by
eddieh-xlnx
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Draft
[DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA
#1137
opened Jan 13, 2025 by
eddieh-xlnx
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Draft
[RWRoute] Adjust wire base costs + cross SLR estimates
#1030
opened Jul 12, 2024 by
eddieh-xlnx
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Draft
[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017
opened Jun 25, 2024 by
clavin-xlnx
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Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011
opened Jun 21, 2024 by
clavin-xlnx
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Node.getAllWiresInNode() returns empty list when Vivado doesn't
bug
#1002
opened Jun 12, 2024 by
eddieh-xlnx
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Draft
[DeviceResourcesWriter] Output resource timings for US+
#1001
opened Jun 12, 2024 by
eddieh-xlnx
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Draft
Adds a tieoff method for module instances with unconnected inputs
#811
opened Sep 7, 2023 by
clavin-xlnx
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Inconsistent behaviour for Cell.getSitePinFromLogicalPin()
bug
#473
opened Jul 14, 2022 by
eddieh-xlnx
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Draft
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Updated in the last three days: updated:>2025-11-12.