Merge remote-tracking branch 'upstream/master' into rwroute_cleanup

Author: eddieh-xlnx

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.3.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2025.1.0.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.3-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2025.1.0-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2024.2.3-beta
+  RAPIDWRIGHT_VERSION: v2025.1.0-beta
 
 jobs:
   build:

RELEASE_NOTES.TXT

@@ -1,4 +1,34 @@
-============= RapidWright 2024.2.3-beta released on 2025-5-29 ================
+============= RapidWright 2025.1.0-beta released on 2025-06-25 ================
+Notes:
+  - Add methods to access internal DiffMap (#1234)
+  - [EDIFNetlist] Update library when renaming cells; add API to remove blackbox prop (#1226)
+  - Fixes to count LOOKAHEAD8 cells in Versal designs (#1230)
+  - [NetlistBrowser] Fix extra click issue with instances (#1229)
+  - [Netlist Browser] GUI Widget to browse a loaded netlist (#1225)
+  - [CopyImplementation] Command-line version of DesignTools.copyImplementation() (#1215)
+  - [DesignTools.copyImplementation()] Support Versal IMR routethrus (#1224)
+  - [ECOTools] connectNet() remove static net assertion (#1223)
+  - [ECOTools] Fix connectNet() for pins that don't need routing (#1222)
+  - [LUTTools] Properly size LUTCY* primitives (#1221)
+  - [LUTInputConeOpt] Enable unplaced netlists (#1213)
+  - [PhysNetlistWriter] Treat bidir BEL pins on PS8 as output (#1214)
+  - [ECOTools] Augments connectNet() to handle dual-LUT pin usage scenarios (#1209)
+  - Basic VS Code Settings (#1210)
+  - LUT Input Cone Optimization (#1205)
+  - Design Obfuscator - Flattens design and uses hashing to obfuscate names (#1196)
+  - Regroup Instances -- command line tool (#1201)
+  - [PartialDFXRouter] Add PartialRouter specialization for DFX designs (#1204)
+  - [RWRoute] Connection.setAllTargets() to always set primary sink (#1206)
+  - [ECOPlacementHelper] Fix NPE for getUnusedFlop() (#1207)
+  - [Actions] Remove gradle/wrapper-validation-action (#1208)
+  - [RWRoute] Minor cleanup (#1203)
+  - [Design.createModuleInst()] Handles black boxes by renaming prior to Design.addModule() 
+  - Fixes gap routing issue
+  - Improves NOC traffic parsing file
+
+API Additions:
+  - (None)
+============= RapidWright 2024.2.3-beta released on 2025-05-29 ================
 Notes: 
   - Add testcase for #780 (Design.routeSites()) (#1191)
   - Post-route fanout optimization (#1178)
@@ -31,7 +61,7 @@ API Additions:
   - com.xilinx.rapidwright.design.Design "public List<PartitionPin> getPartitionPins(Net net)"
   - com.xilinx.rapidwright.design.Design "public Net getNetFromPartitionPin(PartitionPin p)"
 
-============= RapidWright 2024.2.2-beta released on 2025-3-25 ================
+============= RapidWright 2024.2.2-beta released on 2025-03-25 ================
 Notes: 
   - [DesignTools] Fix routethru corner case in fullyUnplaceCellHelper() (#1157)
   - Add option to uniquify copied cells (#1156)
@@ -49,7 +79,7 @@ API Additions:
   - com.xilinx.rapidwright.design.Design "public static Map<SiteTypeEnum, Set<String>> getCompatiblePlacements(FamilyType family, Unisim u)"
 
 
-============= RapidWright 2024.2.1-beta released on 2025-1-15 ================
+============= RapidWright 2024.2.1-beta released on 2025-01-15 ================
 Notes: 
   - Adds an Override Flag for Advanced Flow Settings in Designs (#1135)
   - Test for SiteInst.isEmpty() (#1128)

python/setup.py

@@ -24,7 +24,7 @@
 
 setup(
     name='rapidwright',
-    version='2024.2.3',
+    version='2025.1.0',
     license='Apache 2.0 and Others',
     description='Xilinx RapidWright Framework Wrapped for Python.',
     long_description='',

python/src/rapidwright/rapidwright.py

@@ -24,7 +24,7 @@
 from typing import List, Optional
 import os, urllib.request, platform
 
-version='2024.2.3'
+version='2025.1.0'
 
 def start_jvm():
     os_str = 'lin64'

src/com/xilinx/rapidwright/design/DesignTools.java

@@ -693,6 +693,8 @@ public static Map<UtilizationType, Integer> calculateUtilization(Collection<Site
                     incrementUtilType(map, UtilizationType.REGS_AS_FFS);
                 } else if (belName != null && belName.contains("CARRY")) {
                     incrementUtilType(map, UtilizationType.CARRY8S);
+                } else if (belName != null && belName.equals("LOOKAHEAD8")) {
+                    incrementUtilType(map, UtilizationType.LOOKAHEAD8);
                 }
             }
             for (char letter : LUTTools.lutLetters) {
@@ -3149,11 +3151,18 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
                         if (tmpCell.isRoutethru()) {
                             String cellName = tmpCell.getName();
                             String prefixMatch = StringTools.startsWithAny(cellName, prefixes.keySet());
+                            boolean keepPhysName = false;
                             if (prefixMatch == null) {
-                                throw new RuntimeException("ERROR: Unable to find appropriate "
-                                    + "translation name for cell: " + tmpCell);
+                                BEL bel = tmpCell.getBEL();
+                                if (bel.isIMR() || bel.isCEIMR() || bel.isSRIMR()) {
+                                    keepPhysName = true;
+                                } else {
+                                    throw new RuntimeException("ERROR: Unable to find appropriate "
+                                            + "translation name for cell: " + tmpCell);
+                                }
                             }
-                            String newCellName = getNewHierName(cellName, srcToDestNames, prefixes, prefixMatch);
+                            String newCellName = keepPhysName ? cellName
+                                    : getNewHierName(cellName, srcToDestNames, prefixes, prefixMatch);
                             Cell rtCopy = tmpCell
                                     .copyCell(newCellName, tmpCell.getEDIFHierCellInst(), dstSiteInst);
                             dstSiteInst.getCellMap().put(belName, rtCopy);

src/com/xilinx/rapidwright/design/Unisim.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Advanced Micro Devices, Inc.
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -33,7 +33,7 @@
 import com.xilinx.rapidwright.edif.EDIFLibrary;
 
 /**
- * Generated on: Thu Nov 21 13:34:09 MST 2024
+ * Generated on: Sat Jun 07 20:43:57 MDT 2025
  * by: com.xilinx.rapidwright.release.UnisimParser
  *
  * Enumerates supported Unisim primitives that map to Xilinx devices.
@@ -180,6 +180,7 @@ public enum Unisim {
     DDRMC5,
     DDRMC5C,
     DDRMC5E,
+    DDRMC5X,
     DDRMC_RIU,
     DFE_CFR,
     DFE_CHANNELIZER,
@@ -700,6 +701,7 @@ public enum Unisim {
     LDP_1,
     LD_1,
     LOOKAHEAD8,
+    LPDDRMC,
     LUT1,
     LUT1_D,
     LUT1_L,
@@ -1201,6 +1203,7 @@ public enum Unisim {
     PCIE40E4,
     PCIE40E5,
     PCIE4CE4,
+    PCIE4CEE4,
     PCIE50E5,
     PCIE_2_1,
     PCIE_3_0,
@@ -1215,11 +1218,14 @@ public enum Unisim {
     PLLE2_BASE,
     PLLE3_ADV,
     PLLE3_BASE,
+    PLLE4XP_ADV,
+    PLLE4XP_BASE,
     PLLE4_ADV,
     PLLE4_BASE,
     PLL_ADV,
     PLL_BASE,
     PS11,
+    PS11_A,
     PS7,
     PS8,
     PS9,
@@ -1389,6 +1395,9 @@ public enum Unisim {
     XORCY,
     XORCY_D,
     XORCY_L,
+    XP5IO_VREF,
+    XP5PHY_HS,
+    XP5PHY_LS,
     XPHY,
     XPIO_VREF,
     XPIPE_QUAD,

src/com/xilinx/rapidwright/design/blocks/UtilizationType.java

@@ -49,7 +49,8 @@ public enum UtilizationType {
     RAMB36S_FIFOS("RAMB36s/FIFOs"),
     RAMB18S("RAMB18s"),
     URAMS("URAMs"),
-    DSPS("DSPs");
+    DSPS("DSPs"),
+    LOOKAHEAD8("LOOKAHEAD8");
 
     private String name;
 

src/com/xilinx/rapidwright/device/FamilyType.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Advanced Micro Devices, Inc.
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Thu Nov 21 13:06:39 MST 2024
+ * Generated on: Wed Jun 11 09:41:43 MDT 2025
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Set of all Supported Xilinx families in RapidWright
@@ -66,12 +66,15 @@ public enum FamilyType {
         QZYNQUPLUS,
         QZYNQUPLUSRFSOC,
         SPARTAN7,
+        SPARTANUPLUS,
         VERSAL,
         VERSALAICORE,
         VERSALAIEDGE,
+        VERSALAIEDGE2,
         VERSALHBM,
         VERSALPREMIUM,
         VERSALPRIME,
+        VERSALPRIME2,
         VIRTEX7,
         VIRTEXU,
         VIRTEXUPLUS,

src/com/xilinx/rapidwright/device/IntentCode.java

@@ -130,7 +130,16 @@ public enum IntentCode {
     NODE_SLL_DATA,
     NODE_GLOBAL_VDISTR_LVL3,
     NODE_GLOBAL_VDISTR_LVL21,
-    NODE_GLOBAL_VDISTR_SHARED;
+    NODE_GLOBAL_VDISTR_SHARED,
+    
+    // Versal Gen 2
+    NODE_GLOBAL_HDISTR_SLOW,
+    NODE_GLOBAL_HDISTR_MED,
+    NODE_GLOBAL_HDISTR_FAST,
+    NODE_GLOBAL_HROUTE_SLOW,
+    NODE_GLOBAL_HROUTE_MED;
+    
+    
 
 
     public static boolean isLongWire(Tile tile, int wire) {