Test Cell.getAllCorrespondingSitePinNames() on Versal

Signed-off-by: Eddie Hung <[email protected]>

Author: eddieh-xlnx

test/src/com/xilinx/rapidwright/design/TestCell.java

@@ -43,6 +43,8 @@ public class TestCell {
             "xcvu3p,SLICE_X0Y0,CARRY8,DI[2],DI2,'[C1, C2, C3, C4, C5]'",
             "xcvu3p,SLICE_X1Y0,CARRY8,S[7],S7,'[H1, H2, H3, H4, H5, H6]'",  // SLICEM
             "xcvu3p,SLICE_X1Y0,CARRY8,DI[3],DI3,'[D1, D2, D3, D4, D5]'",
+            // Versal input pins
+            "xcvp1502,SLICE_X148Y0,B6LUT,I1,A1,'[B1]'",
 
             // Output pins (single logical pin has options to drive many site pins)
             "xcvu3p,SLICE_X0Y0,E6LUT,O,O6,'[E_O, EMUX]'",