Initialization of LUT value and Port Connection on my RW design

[alimousios98x]

1. I am trying to initialize the launch Flip Flop to have the value 0 at the start when the bitstream programs the device (so the first value it will have as an output will be 0 and then it will change every time cause of the new input it will receive via the inverter). I can create the lut and connect it with nets etc but I'm not sure how to do this so that the initialisation lasts only for the first rising edge.

2. Secondly I want to connect the alarm to a certain register or an output port so I get each value it has every clock edge and I haven't been successful so far. You mentioned that I need these two commands ( create_cell to instantiate the IO and connect it to the net with connect_net). Could you help me with this, perhaps an example with some made up IO port to connect the alarm.

My RapidWright code:

package com.xilinx.rapidwright.examples;
import com.xilinx.rapidwright.design.Cell;
import com.xilinx.rapidwright.design.Design;
import com.xilinx.rapidwright.design.Module;
import com.xilinx.rapidwright.design.ModuleInst;
import com.xilinx.rapidwright.design.Net;
import com.xilinx.rapidwright.design.NetType;
import com.xilinx.rapidwright.design.Unisim;
import com.xilinx.rapidwright.device.Device;
import com.xilinx.rapidwright.device.Site;
import com.xilinx.rapidwright.edif.EDIFCell;
import com.xilinx.rapidwright.edif.EDIFDirection;
import com.xilinx.rapidwright.edif.EDIFNet;
import com.xilinx.rapidwright.edif.EDIFPort;
import com.xilinx.rapidwright.router.Router;

public class circuit1 {

    private static final String CLK_NAME = "clk";

    private static final int CHAIN_LENGTH = 3;

    public static Cell createFDRE(Design d, String name, String loc) {
        Cell fdre = d.createAndPlaceCell(name, Unisim.FDRE, loc);
        Net clk = d.getNet(CLK_NAME);
        if (clk == null) {
            clk = d.createNet(CLK_NAME);
            EDIFPort topPortClk = d.getTopEDIFCell().createPort(CLK_NAME, EDIFDirection.INPUT, 1);
            clk.getLogicalNet().createPortInst(topPortClk);
        }
        clk.connect(fdre, "C");
        fdre.connectStaticSourceToPin(NetType.VCC, "CE");
        fdre.connectStaticSourceToPin(NetType.GND, "R");
        return fdre;
    }

    public static void main(String[] args) {
        String partName = "xc7a35tftg256-2";

        // Create some common variables
        Design d = new Design("circuit", partName);
        d.setAutoIOBuffers(false);
        d.setDesignOutOfContext(true);
        EDIFCell top = d.getNetlist().getTopCell();

        Cell launch = createFDRE(d, "launch", "SLICE_X48Y80/AFF");
        Cell capture1 = createFDRE(d, "capture1", "SLICE_X48Y80/BFF");
        Cell capture2 = createFDRE(d, "capture2", "SLICE_X48Y80/CFF");

        Cell inv = d.createAndPlaceCell("inv", Unisim.LUT1, "SLICE_X48Y80/A6LUT");
        inv.addProperty("INIT", "2'h1"); // Inversion
        Net invOut = d.createNet("invOut");
        invOut.connect(launch, "D");
        invOut.connect(inv, "O");
        Net launchOut = d.createNet("launchOut");
        launchOut.connect(launch, "Q");
        launchOut.connect(capture2, "D");
        launchOut.connect(inv, "I0");

        String[] lutNames = {"/A6LUT", "/B6LUT", "/C6LUT", "/D6LUT"}; // Array of LUT names

        // Create delay chain
        Cell[] delays = new Cell[CHAIN_LENGTH];
        Net[] delayOutputs = new Net[CHAIN_LENGTH];
        for (int i = 0; i < CHAIN_LENGTH; i++) {
            delays[i] = d.createAndPlaceCell("delay" + i, Unisim.LUT1,
                    "SLICE_X49Y80" + lutNames[i]);
            delays[i].addProperty("INIT", "2'h0");
            delayOutputs[i] = d.createNet("delayOutput_" + i);
            delayOutputs[i].connect(delays[i], "O");
            if (i == 0) {
                launchOut.connect(delays[i], "I0");
            } else {
                delayOutputs[i - 1].connect(delays[i], "I0");
            }
        }
        delayOutputs[delays.length - 1].connect(capture1, "D");

        Cell xor = d.createAndPlaceCell("xor", Unisim.XOR2, "SLICE_X48Y80/B6LUT");
        Net capture1Out = d.createNet("capture1Out");
        capture1Out.connect(capture1, "Q");
        capture1Out.connect(xor, "I0");
        Net capture2Out = d.createNet("capture2Out");
        capture2Out.connect(capture2, "Q");
        capture2Out.connect(xor, "I1");

        Net alarm = d.createNet("alarm");
        alarm.connect(xor, "O");
        alarm.getLogicalNet().createPortInst(top.createPort("alarm", EDIFDirection.OUTPUT, 1));

        d.routeSites();
        new Router(d).routeDesign();

        // d.writeCheckpoint(d.getName() + ".dcp");

        // Load a top-level design
        Design topDesign = Design.readCheckpoint("D:/ALEXANDROS/Documents/PROJECT/designAES.dcp");

        // Instantiate the created circuit inside our topDesign just loaded
        ModuleInst mi = topDesign.createModuleInst(d.getName(), new Module(d));
        mi.placeOnOriginalAnchor();

        // Connect up the clock
        EDIFNet clkNet = topDesign.getTopEDIFCell().getNet("crypt_clk");
        clkNet.createPortInst("clk", mi.getCellInst());

        topDesign.writeCheckpoint("D:/ALEXANDROS/Documents/PROJECT/COMB1.dcp");

    }
}

For context if it helps, the circuit:

[TotoroTron]

I am also still learning how to use this API, so this is a learning opportunity for me:

1. I think your goal here is to define the LUT's truth table, not its "initial value". In my understanding, you can only define initial values for flip flop outputs. The flip flop initial outputs propagate through LUTs and that's how LUTs get their "initial output values".

With that being said, the below statement correctly sets your "inv" LUT1 truth table to the expression: "O=!I0"

inv.addProperty("INIT", "2'h1");

However, this next statement sets your "delay" LUT1 truth tables to: "O=0", meaning the output is always 0 regardless of I0's value.

delays[i].addProperty("INIT", "2'h0");

There may or may not be a correct way to initialize the LUT truth table via .addProperty(), but the API does have a function to explicitly define the truth table as a sum of minterms equation via LUTTools::configureLUT(Cell c, String equation) like this:

        for (int i = 0; i < CHAIN_LENGTH; i++) {
            delays[i] = d.createAndPlaceCell("delay" + i, Unisim.LUT1,
                    "SLICE_X49Y80" + lutNames[i]);

            // Define the truth table using sum of minterms expression
            LUTTools.configureLUT(delays[i], "O=I0");
            System.out.println("delay[" + i + "] truth table: " +
                    LUTTools.getLUTEquation(delays[i]));

            // delays[i].addProperty("INIT", "2'h0");
            delayOutputs[i] = d.createNet("delayOutput_" + i);
            delayOutputs[i].connect(delays[i], "O");
            if (i == 0) {
                launchOut.connect(delays[i], "I0");
            } else {
                delayOutputs[i - 1].connect(delays[i], "I0");
            }
        }

This should initialize your "delay" LUT1 with the equation "O=I0" instead of "O=0".

https://www.rapidwright.io/javadoc/com/xilinx/rapidwright/design/tools/LUTTools.html

2. If you want to route the alarm Net to a physical IO port, you can use Design::createAndPlaceIOB like so:

        Cell xor = d.createAndPlaceCell("xor", Unisim.XOR2, "SLICE_X48Y80/B6LUT");

        //
        // your existing code
        //

        Net alarm = d.createNet("alarm");
        alarm.connect(xor, "O");
        
        // change "D5" to whichever package pin you want.
        Cell obuf = d.createAndPlaceIOB("obuf", PinType.OUT, "D5", "LVCMOS33");
        System.out.println("Created cell: " + obuf.getName() + ", at Site: " + obuf.getSite().getName());
        alarm.connect(obuf, "I");

        d.routeSites();
        new Router(d).routeDesign();

You should be able to see the new OBUF cell in the Schematic/Device windows.

https://www.rapidwright.io/javadoc/com/xilinx/rapidwright/design/Design.html#createAndPlaceIOB-java.lang.String-com.xilinx.rapidwright.design.PinType-java.lang.String-java.lang.String-

You can find more simple IO examples here:
https://github.com/Xilinx/RapidWright/blob/master/src/com/xilinx/rapidwright/examples/Lesson1.java

[alimousios98x]

1. I might have described my needs somewhat complicated. Below I have attached the design in question. I want the launch Flip-Flop to have a starting value 0 or 1 which will then pass to my inverter ( hence the inv.addProperty("INIT", "2'h1"); // Inversion ) and my other paths leading to the alarm and the launch Flip-Flop will keep passing different values every pulse cause of the inverter. All this logic is implemented but I cant figure out how to have the launch flip flop have a "starting-value" once at the start of the device programming. I do not wish to do anything else with the delay LUTS other than use them as buffers to pass values.

Below is the way to do this in Vivado for example but i want to do this initialization through RW since i create this Flip-Flop the same way.

2. I don't wish to see an actual alarm. I just want the value the alarm will have every pulse in an array to see. Perhaps this will work the same way with a relevant port conencted.

[TotoroTron]

1. I cant figure out how to have the launch flip flop have a "starting-value" once at the start of the device programming

I think you can also use .addProperty() on the FDRE cell to set the intial value.
When you create the FDRE cell named "launch", can you try this?

Cell launch = createFDRE(d, "launch", "SLICE_X48Y80/AFF");
launch.addProperty("INIT", "1'b1");

Or set to "1'b0" if you want to initialize to zero. I would have thought FDREs are initialized to zero by default, is that not the case?