Creating Empty PBlocks in a .DCP for Future Noise Logic Insertion

[EirGalid]

I'm trying to create a .dcp file that will contain areas for noise generators around or inbetween specific operations of an algorithm. Initially, I would like to create a simple .dcp that will only contain empty pblocks, which need to be kept empty, so that my noise logic can be added later from another .dcp (perhaps using merge). Basically, the algorithm will be implemented around those pblocks and only the generators will be inside the pblocks.

Perhaps I don't fully understand the documentation referring to PBlock creation, but is it better to use setLocked, "fixed" flag, or something else entirely? As far as I understand, "DONT_TOUCH" is only used if there is a netlist or pins.

My alternative (and probably the easiest way to do this, avoiding RW) would be to create the pblocks using Vivado and then exporting the .dcp, but I'm interested in trying to do this using RW if possible.

[clavin-xlnx]

It sounds like you'd like to compose two or more placed and routed circuit together into a single implementation. You can certainly accomplish this with either Vivado or RapidWright with some variation based on the scenario. Perhaps we can define a few terms just to align our understanding:

• pblock - A pblock is an area constraint that restricts placement and/or routing of a circuit to a specific area of the FPGA fabric. A pblock does not have any impact on the netlist or hierarchy of logic in the design, it simply affects placement and routing.
• The API Cell.setLocked() isn't actually used much and probably isn't the flag you'd want to use
• The "fixed" flag is referring to preventing specific Cell objects from being moved. In Vivado, this can be accomplished with setting two flags on a cell simultaneously called IS_BEL_FIXED and IS_LOC_FIXED, with these Tcl commands:

set_property is_bel_fixed true [get_cells <cell>]
set_property is_loc_fixed true [get_cells <cell>]

• A design can also be "locked" at different levels (post-synth, post-place, post-route) using lock_design.
• DONT_TOUCH is a synthesis directive that is applied to logic elements, often modules to prevent changes during synthesis.

Although I'm not sure I completely understand your design goals, one way to approach this effort is to start with a high-level design that includes all the logic you want in your final implementation. Partition the logic and hierarchy into specific modules (each noise generator, operation or algorithm gets its own module). Once you have a top level design, you can apply a pblock to each module to match how you want the logic to be placed and routing in the different areas of the FPGA fabric.

If you want to swap out the guts of a module with noise logic, you can use either Vivado or RapidWright depending on the requirements. Generally, if you can use Vivado, that might be the easiest. You can swap out logic of a module by turning it into a black_box first and the re-populating it with the contents of a DCP with read_checkpoint -cell. For example, suppose you have a design with module "noise_logic" which has a dummy circuit, but you want to swap it out with the contest of another DCP. You could do the following:

update_design -cells noise_logic -black_box
read_checkpoint -cell noise_logic my_new_noise_logic.dcp

Be sure to also read up on how pblocks work in Vivado and their associated properties CONTAIN_ROUTING and EXCLUDE_PLACEMENT here: https://docs.amd.com/r/en-US/ug912-vivado-properties/PBLOCK.

[EirGalid]

Thanks for the reply. I was interested in seeing how my algorithm would be optimized and implemented around those empty pblocks, before occupying those spaces with my noise logic. I'll try using modules instead and maybe stick to Vivado for this one.