Re-routing nets

[sma-asghar]

Hi,
I am trying to reroute a net on an implemented dcp. The net has several sink pins. I want to disconnect this net from its sinks and re-route it to through a chain of LUTs (say an inv. and a XOR). Also, these changes shouldn't affect the rest of the routing.

I have already created my LUT cells and the nets to connect these LUTs. Also, I collected the pips b/w the source pin of the target net and all its sinks. I am not sure how to disconnect the target net from its sinks and connect the sinks to the output of the last LUT of the chain. Also, is there already an example somewhere showing the steps to perform custom changes to a routed design?

Regards,
Ali

[eddieh-xlnx]

Hi @sma-asghar. It seems like you're trying to achieve a sequence of tasks:

1. Disconnect and unroute a routed net from one-or-more sinks in both its logical (EDIF) and physical netlists.
2. Create and place a chain of LUTs.
3. Connect the original net through these LUTs (creating/connecting intermediate nets as necessary)
4. Connect the final net emanating from the last LUT in your chain to the original sinks.

It sounds like you've already done 2. For the rest, I would suggest you look at the ECOTools package, which contains a number of methods like connectNet() and disconnectNet() (that mirror Vivado's connect_net and disconnect_net Tcl commands).

Also, is there already an example somewhere showing the steps to perform custom changes to a routed design?

The tutorial at https://www.rapidwright.io/docs/ECO_Insert_Route_Debug.html shows how those ECOTools.connectNet() can be used on a routed design.

If you need further guidance, or you run into any problems with ECOTools, please let us know.

[sma-asghar]

Thanks for your reply @eddieh-xlnx.
Here is my code:

import rapidwright
from com.xilinx.rapidwright.design import Unisim
from com.xilinx.rapidwright.design import Design
from com.xilinx.rapidwright.design import DesignTools
from com.xilinx.rapidwright.design.tools import LUTTools
from com.xilinx.rapidwright.eco import ECOTools


design = Design.readCheckpoint("./minimal.dcp")
dev = design.getDevice()

targetNet = design.getNet('r_b')
srcNode = targetNet.getSource().getConnectedNode()

detourTile = targetNet.getSourceTile()
detourNode = dev.getNode(str(detourTile) + '/' + 'CLBLL_L_C6')
detourSite = targetNet.getSource().getSiteInst().getSite().getNeighborSite(1,0)

lutINV = design.createAndPlaceCell("inv_LUT",Unisim.LUT1,str(detourSite)+'/C6LUT')
lutINV.addProperty("INIT", "2'h1")
netINV = design.createNet('inv_out')
netINV.connect(lutINV, 'O')

lutSink = design.getCell('o_i_1')
lutSinkPin = lutSink.getSiteInst().getSitePinInst('A6')

ECOTools.connectNet(design, lutINV, 'I0', design.getNet('r_b'))
hier_net = targetNet.getLogicalHierNet()
port_hier = hier_net.getLeafHierPortInsts()

#Disconnecting the sink pin from targetNet:
ECOTools.disconnectNet(design,port_hier[1])

#Now connecting the INV output to the sink pin
ECOTools.connectNet(design, lutSink, 'I0', netINV)

targetNet.lockRouting()
netINV.lockRouting()

design.writeCheckpoint("./customRoute_inv.dcp")

The generated dcp (in Vivado) shows the status of both nets as 'Routable but not routed'. I can see the Site wires (in red) for the newly created net connections, however, the nets (r_b and netINV) are not fully routed.

[eddieh-xlnx]

Can you share minimal.dcp please?

[sma-asghar]

minimal.zip

[clavin-xlnx]

Hi @sma-asghar, thanks for sharing the example design. It looks like you are doing everything right, the only thing left to do is route the site with the added inverter and route the new nets. The APIs in ECOTools do not do any of the physical routing (what Vivado does during route_design).

I was able to get a fully routed design by adding the following lines (I included additional lines from your code for context):

import rapidwright
#...
from com.xilinx.rapidwright.router import Router
#...

#Now connecting the INV output to the sink pin
ECOTools.connectNet(design, lutSink, 'I0', netINV)

# We need site routing updated after connecting the INV to the nets
lutINV.getSiteInst().routeSite()
# This is the basic RapidWright router to route the unrouted connections
Router(design).routeDesign()

targetNet.lockRouting()
netINV.lockRouting()

design.writeCheckpoint("./customRoute_inv.dcp")

After loading up customRoute_inv.dcp in Vivado and running report_route_status I get:

Design Route Status
                                               :      # nets :
   ------------------------------------------- : ----------- :
   # of logical nets.......................... :          15 :
       # of nets not needing routing.......... :           7 :
           # of internally routed nets........ :           7 :
       # of routable nets..................... :           8 :
           # of nets with fixed routing....... :           2 :
           # of fully routed nets............. :           8 :
       # of nets with routing errors.......... :           0 :
   ------------------------------------------- : ----------- :

One note about routing -- the Router class, although it works with Series 7 devices, is not extremely robust. It is convenient for quick and dirty routes, but doesn't scale well. We have a more robust router called RWRoute that can handle larger designs, has a timing driven mode, but doesn't support Series 7 (it supports UltraScale+ and Versal).

Let us know if you have other questions.

[sma-asghar]

Thanks for your reply Chris. Yes, I figured out that the intra-site routing was missing in my code.
The provided code works. However, I ran into another problem when using ECOTools.connectNet(). If the sinkpin of the targetNet happens to be a shared input of a LUT6_2, the connectNet() fails when it tries to connect the output of the inverter to the sinkpin of the original net.
ERROR: Site pin SLICE_X12Y135.A1 cannot be used to connect to logical pin: top/data_o[100]/I0' since it is also connected to pin 'top/data_o[99]/I0'

[clavin-xlnx]

Would you mind sharing with us a test case? I tried to reproduce on one of our test designs:

        Design d = Design.readCheckpoint("test/RapidWrightDCP/microblazeAndILA_3pblocks_2024.1.dcp");
        Net newNet = d.getNet("base_mb_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Gen_Bit[11].MUXF7_I1/Using_FPGA.Native_i_2__123_n_0");
        // This cell is part of a LUT6_2
        Cell cell = d.getCell("base_mb_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[10].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6");
        ECOTools.connectNet(d, cell, "I0", newNet);
        d.writeCheckpoint("microblaze_eco.dcp");

But didn't get the error you are seeing.
Original:

Post ECOTools.connectNet():

[sma-asghar]

Thanks for your reply Chris. I have attached a dcp file, which is an extension of the minimal example shared earlier.

Here is my code which results in the mentioned error:

import rapidwright
from com.xilinx.rapidwright.design import Unisim
from com.xilinx.rapidwright.design import Design
from com.xilinx.rapidwright.eco import ECOTools

design = Design.readCheckpoint("./minimal_route_2023.dcp")
dev = design.getDevice()
detourSite = targetNet.getSource().getSiteInst().getSite().getNeighborSite(1,0)

lutINV = design.getCell('inv_LUT')

targetNet = design.getNet('r_b')
hier_net = targetNet.getLogicalHierNet()
port_hier = hier_net.getLeafHierPortInsts()

lutINT = design.createAndPlaceCell("int_LUT",Unisim.LUT1,str(detourSite)+'/A6LUT')
lutINT.addProperty("INIT", "2'h1")

netINT = design.createNet('int_out')
netINT.connect(lutINT, 'O')

#Connecting the targetNet to the lutINV:
ECOTools.connectNet(design, lutINT, 'I0', targetNet)

#Connecting the o/p of intINV to LUTINV:
ECOTools.connectNet(design, lutINV, 'I0', netINT)

lutINV.getSiteInst().routeSite()

design.writeCheckpoint("./minimal_routed_mod.dcp")

minimal_route_2023.zip

[sma-asghar]

Apologies for the mistakes in the comments.
They should be:

#Connecting the targetNet to the lutINT:
ECOTools.connectNet(design, lutINT, 'I0', targetNet)

#Connecting the o/p of lutINT to LUTINV:
ECOTools.connectNet(design, lutINV, 'I0', netINT)

[clavin-xlnx]

Thanks for the example! It doesn't look like there is a LUT6_2 instantiated, but the issue does stem from multiple LUTs placed on the same LUT complex. The problem is that inv_LUT and fwd_LUT are both using the physical pin A2 as an input. In the original design, there isn't a problem but because we now want to connect inv_LUT's I0 to the int_out net instead of r_b which it is currently connected to, there is a conflict:

What needs to happen is that we need to identify a new physical pin now that the I0 pin is being differentiated and no longer shares the same input as its companion LUT fwd_LUT. We need to remove the pin mapping on lut_INV for A2 and use another physical pin instead. For example, a quick work around for this scenario is:

        lutINV.removePinMapping("A2")
        lutINV.addPinMapping("A5", "I0")

We can automate this process, but will take a little bit to test and deploy, stay tuned!

[clavin-xlnx]

@sma-asghar - I've created a fix for so that ECOTools.connectNet() should handle this scenario. Also, you'll want to augment the code so that before you connect a pin to a net, it must be disconnected first. For example, you'll want use ECOTools.disconnectNet() first:

        ECOTools.disconnectNet(design, lutINV.getEDIFHierCellInst().getPortInst("I0"));
        ECOTools.connectNet(design, lutINV, "I0", netINT);

[eddieh-xlnx]

@sma-asghar - I've created a fix for so that ECOTools.connectNet() should handle this scenario.

The fix (for connecting to dual LUTs) at #1209 has now been merged into master. Let us know how you get along!