Issue with connecting previously removed cell pins to net

[chrmarlyn]

Hi,

I am trying to learn how to use RapidWright—more specifically how to create and manage nets. One of the test cases that I tried was to remove and re-add an existing net. These are the steps that I took:

1. Create a new design from scratch with two LUT 6s and a net connecting the two
2. Writing a checkpoint
3. Loading that checkpoint
4. Removing the source and sinks of the target net
5. Removing the net from the loaded design
6. Creating a new net
7. Connecting the same pins (plus an extra pin for testing) to the net using Net.connect()

However, when I try to print the nets present in the design after step 7, I get the following output in my Python terminal:

(Before removal)
Pins before sink removal: [OUT SLICE_X100Y0.A_O, IN SLICE_X100Y0.B6]
Pins before source removal: [OUT SLICE_X100Y0.A_O]
Remaining pins: []
Target net 'old_net' was succesfully removed

(After re-adding the net)
Net name: new_net Source: None Sinks: [IN SLICE_X100Y0.B1]

As you can see, only the extra pin (which wasn't a part of the old net) is successfully connected to the new net, whereas the ones that I am trying to re-use (O and I5 in my code) don't get connected at all (and without any error messages from the library). Am I doing something wrong or could this possibly be a bug? The only solution I found to it was to write and load a new checkpoint between step 5 and 6, but this doesn't feel like a sustainable option for larger designs. The board that I am using for my design is the Virtex UltraScale+ (xcvu19p-fsva3824-2-e).

Below is my full code. Sorry for advance if the my question is weirdly formatted. This is the first time I am posting on GitHub!

I appreciate any help I can get :)

/Chrysella

Edit: It is worth mentioning that the line loadedDesign.routeSites() throws the following exceptions (hence why it has been commented out):

WARNING: Could not find parent of net "new_net", please check that the netlist is fully connected through all levels of hierarchy for this net.
Traceback (most recent call last):
  File "com.xilinx.rapidwright.design.Design.java", line 0, in com.xilinx.rapidwright.design.Design.routeSites
Exception: Java Exception

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  File "dummy_test.py", line 85, in <module>
    loadedDesign.routeSites()
java.lang.java.lang.NullPointerException: java.lang.NullPointerException: Cannot invoke "com.xilinx.rapidwright.edif.EDIFHierNet.getNet()" because "<local4>" is null

This seems to indicate that the net new_net doesn't actually get added to the design or is added incorrectly, but I have trouble understanding why. Please do correct me if I'm wrong!

Code:

import rapidwright

from com.xilinx.rapidwright.design import Design, Unisim, tools
from com.xilinx.rapidwright.router import Router
from com.xilinx.rapidwright.rwroute import PartialRouter

"Uncomment and run once to write the DCP file"

# design = Design("dummy", "xcvu19p-fsva3824-2-e")

# cells = []

# # Place 2 LUTs
# for i in range(0,2):
#     new_cell = design.createAndPlaceCell("test_LUT6_" + str(i), Unisim.LUT6, "SLICE_X100Y0/" + chr(65+i) + "6LUT")
#     tools.LUTTools.configureLUT(new_cell, "O=I5")
#     cells.append(new_cell)

# # Net to be removed, connects the two LUTs
# old_net = design.createNet("old_net")
# old_net.connect(cells[0], "O")
# old_net.connect(cells[1], "I5")

# #design.addNet(old_net)

# # Intra- and inter-site routing
# design.routeSites()
# Router(design).routeDesign()

# # Check the nets
# print("Current net(s):", design.getNets())

# # for net in design.getNets():
# #     for pin in net.getPins():
# #         print("Net:", net, "Pin:", pin.getName())


# "Export DCP file"
# #design.writeCheckpoint("dummy_exp.dcp")

"------------------------------------------------------------------------------------------------------------------------------------"

"Import DCP file"
loadedDesign = Design.readCheckpoint(r"path") # Don't forget to add the file path


"Removal of old net"
# Load the net to remove
target_net = loadedDesign.getNet("old_net")

print("Pins before sink removal:", target_net.getPins())

# Remove sinks
for sink_pin in target_net.getSinkPins():
    target_net.removePin(sink_pin)

print("Pins before source removal:", target_net.getPins())

# Remove source
target_net.removeSource()

# Check all remaining pins
print("Remaining pins:", target_net.getPins())

# Remove net
loadedDesign.removeNet(target_net)

loadedDesign.unrouteDesign()

# Check if net was removed

print( (f"Target net '{target_net.getName()}' was succesfully removed\n") if loadedDesign.getNet(target_net.getName()) == None else "Removal failed")

"Re-add the net"  
new_net = loadedDesign.createNet("new_net")

cell = loadedDesign.getCells()
print("Cells in design are:", cell)

new_net.connect(loadedDesign.getCell("test_LUT6_0"), "O")
new_net.connect(loadedDesign.getCell("test_LUT6_1"), "I0")
new_net.connect(loadedDesign.getCell("test_LUT6_1"), "I5")

# loadedDesign.routeSites()
# Router(loadedDesign).routeDesign()

print("Net name:", new_net.getName(), "Source:", new_net.getSource(), "Sinks:", new_net.getSinkPins())
print("Unrouted pins:", PartialRouter.getUnroutedPins(loadedDesign))

"As seen from the results of the print statements, it is possible to add a brand new pin (I0) to the newly created net,"
"but it is not possible to re-add previously the used pins O and I5."

[clavin-xlnx]

Thanks @chrmarlyn for your example code! You are approaching this in a straight forward way and I think it will help us better document these APIs and how to think about using them. One important thing to understand about RapidWright and designs from Vivado in general is that there is a logical netlist and a physical netlist. In RapidWright, we represent the logical netlist with all of the objects that start with EDIF* (EDIFCell, EDIFPort, EDIFCellInst, EDIFNet, and EDIFPortInst, see this diagram to help map them to what is shown in Vivado's schematic viewer).

The physical netlist is represented by the more generic names such as Cell, Net, SiteInst, SitePinInst. When modifying an implementation, we need to modify both the logical and physical netlist at the same time to keep them in sync. RapidWright allows you to customize how these modifications are made, so some methods will not modify both at the same time, or without context, may not do exactly what is expected.

In short, to connect and disconnect cells from both the logical and physical netlist, the best way to proceed is it use the methods ECOTools.disconnectNet() and ECOTools.connectNet() which effectively handles both logical and physical netlist modifcations. For example:

# ...
from com.xilinx.rapidwright.eco import ECOTools

loadedDesign = Design.readCheckpoint("dummy_exp.dcp")

target_net = loadedDesign.getNet("old_net")

# First remove all the sinks
ECOTools.disconnectNet(loadedDesign, target_net.getLogicalHierNet().getLeafHierPortInsts(False));
# Then remove the source
ECOTools.disconnectNet(loadedDesign, target_net.getLogicalHierNet().getLeafHierPortInsts());
loadedDesign.removeNet(target_net);

new_net = loadedDesign.createNet("new_net");

ECOTools.connectNet(loadedDesign, loadedDesign.getCell("test_LUT6_0"), "O", new_net);
ECOTools.connectNet(loadedDesign, loadedDesign.getCell("test_LUT6_1"), "I0", new_net);
ECOTools.connectNet(loadedDesign, loadedDesign.getCell("test_LUT6_1"), "I5", new_net);

# This router is extremely basic, in most cases you'll want use the RWRoute router (see com.xilinx.rapidwright.rwroute.RWRoute)
Router(loadedDesign).routeDesign();

loadedDesign.writeCheckpoint("final.dcp");

After running this and loading final.dcp in Vivado, I get this schematic (logical netlist):

Here is the Device view (physical netlist):

Hope that helps.

[chrmarlyn]

Hello again Chris,

Thank you so much for the educational reply! It was very helpful :) I really appreciate your help!

Have a nice day!

/Chrysella